How EUV Lithography Machines Work: Tin Plasma, Mirrors and High-NA

An EUV lithography machine prints chip patterns with 13.5 nm light that it makes itself, 50,000 times a second, by hitting falling droplets of molten tin with a CO2 laser. The light is collected, shaped and bounced off a series of molybdenum and silicon multilayer mirrors and a reflective mask, all in vacuum, then projected four times smaller onto a wafer that scans beneath it with sub-nanometre positioning.

This post follows the light through the machine: the tin plasma source and collector, the mirrors, the reflective reticle and pellicle, the vacuum, the stages, overlay, throughput and the stochastic defects that set the practical limit. Then it covers High-NA EUV, the supply chain and export controls. Every computed number was checked with Python, and the scripts are included so you can rerun them.

Safeguard does not design, build, program or speed up lithography machines or any other hardware. Our link to the topic is narrow and comes at the end: the software that fab tools run.

Key takeaways

• The wavelength is 13.5 nm, more than 14 times shorter than the 193 nm argon fluoride light used in deep ultraviolet (DUV) scanners, according to ASML's own technology pages.
• The light comes from tin plasma. Tin droplets about 25 microns across leave a generator at 70 m/s. A weak laser pulse flattens each droplet into a pancake and a strong pulse turns it into plasma that emits EUV. This happens 50,000 times per second.
• Only a few percent of the light reaches the wafer. A peer reviewed source paper from Cymer and ASML works the example of 10 mirror reflections at 67% peak reflectivity and gets about 2% overall transmission. That is why the source needs hundreds of watts.
• Everything is a mirror and everything is in vacuum. EUV is absorbed by almost every material, including air, so there are no lenses, the mask is a reflector, and the whole path from source to wafer is under high vacuum.
• Resolution follows the Rayleigh criterion, CD = k1 · λ / NA. ASML quotes 13 nm resolution for its 0.33 NA systems and 8 nm for its 0.55 NA (High-NA) systems. Both correspond to a k1 of roughly 0.32.
• High-NA EUV uses anamorphic optics that demagnify 4 times in one direction and 8 times in the other. That keeps the standard six-inch mask but halves the exposure field to 26 mm by 16.5 mm, so large dies need stitching.
• Stochastic effects are the practical limit. At 30 mJ/cm2, an EUV exposure delivers about 20 incident photons per square nanometre, against about 290 for 193 nm light at the same dose. Fewer photons means more random variation.
• Throughput is quoted at a stated dose. ASML lists at least 220 wafers per hour at 30 mJ/cm2 for the NXE:3800E, and at least 110 (EXE:5000) and 175 (EXE:5200B) wafers per hour at 50 mJ/cm2 for the High-NA systems.

The machine at a glance

Here is the light path as a text diagram. It is a simplification; ASML has not published a full optical prescription.

   CO2 drive laser (10.6 um, pulsed at about 50 kHz)
        |  beam transport (TRUMPF says up to 30 m)
        v
 +-------------------------------+
 |  SOURCE VESSEL (vacuum + H2)  |
 |  tin droplet generator        |
 |      o  o  o  (70 m/s)        |
 |      prepulse -> pancake      |
 |      main pulse -> plasma *   |
 |  ellipsoidal collector mirror |
 +---------------+---------------+
                 | intermediate focus (IF)
                 v
 +-------------------------------+
 |  ILLUMINATOR (multilayer      |
 |  mirrors shape the pupil and  |
 |  the slit)                    |
 +---------------+---------------+
                 v
 +-------------------------------+
 |  REFLECTIVE RETICLE on the    |
 |  reticle stage (scans fast)   |
 +---------------+---------------+
                 v
 +-------------------------------+
 |  PROJECTION OPTICS            |
 |  multilayer mirrors, 4x       |
 |  reduction (4x / 8x High-NA)  |
 +---------------+---------------+
                 v
 +-------------------------------+
 |  WAFER on a maglev stage,     |
 |  scanning opposite to the     |
 |  reticle; second stage being  |
 |  measured in parallel         |
 +-------------------------------+

ASML's EUV product page breaks the tool into the same blocks: the light source, the optical column, the reticle, the vacuum chamber, the wafer handler and the wafer stage. Its descriptions are short but specific. The source uses "a CO2 laser" that "fires two separate laser pulses at a fast-moving drop of tin". The optical column uses "several multilayer mirrors instead of lenses" and shrinks "the reticle pattern by a factor of four". The reticle is a "multilayer reflector" that uses interference. Because EUV "is absorbed by everything, even air", the whole path "must be in high vacuum". The wafer handler moves wafers through an air lock "within a positioning accuracy of 25 µm" and "a uniform surface temperature within 2 mK", and the wafer stage positions the wafer "to within a quarter of a nanometer for each exposure, checking and adjusting 20,000 times per second".

A short, dated history

The timeline sticks to dates stated in primary sources we fetched. Events whose dates we could not confirm on such a page, such as the closing date of ASML's acquisition of Cymer, are left out.

Why 13.5 nm: the Rayleigh criterion with worked numbers

Every lithography discussion starts with the Rayleigh criterion for the smallest printable feature, usually written as the critical dimension:

CD  = k1 * lambda / NA
DOF = k2 * lambda / NA^2

Here λ is the wavelength, NA is the numerical aperture of the projection optics (a measure of how wide a cone of light the optics can collect and focus), and k1 and k2 are process factors. ASML's "Pushing k1 further" page describes k1 as "a collection of everything else that we can do in the lithography process to enhance the resolution": illumination shape, optical proximity correction, mask design and resist. Textbook optics puts the hard floor for k1 at 0.25 for a periodic line and space pattern, because below that the two diffraction orders needed to form an image no longer both fit through the pupil. Real production processes run comfortably above that floor.

ASML's lenses and mirrors page gives the three NA values that matter. Its highest resolution DUV immersion machines "reach an NA of 1.35", made possible by a layer of water between lens and wafer. Its standard EUV machines run at 0.33. Its High-NA EUV machines run at 0.55. Here is the Rayleigh calculation for all three, at three k1 values, in plain Python. It runs on any machine with Python 3, and we ran it for this post.

# Rayleigh resolution and depth of focus for three exposure regimes.
# Ran on Python 3 for this post; output shown below.
cases = [
    ("ArF immersion", 193.0, 1.35),   # 193 nm, water immersion
    ("EUV NA 0.33",    13.5, 0.33),
    ("High-NA 0.55",   13.5, 0.55),
]

for k1 in (0.25, 0.30, 0.40):
    row = [(name, round(k1 * lam / na, 2)) for name, lam, na in cases]
    print(f"k1={k1}: {row}")

for name, lam, na in cases:
    print(f"{name}: lambda/NA^2 = {lam / na**2:.1f} nm")

# What k1 do ASML's quoted resolutions imply?
print("NXE 13 nm ->  k1 =", round(13 * 0.33 / 13.5, 3))
print("EXE  8 nm ->  k1 =", round(8 * 0.55 / 13.5, 3))

The output:

k1=0.25: [('ArF immersion', 35.74), ('EUV NA 0.33', 10.23), ('High-NA 0.55', 6.14)]
k1=0.3:  [('ArF immersion', 42.89), ('EUV NA 0.33', 12.27), ('High-NA 0.55', 7.36)]
k1=0.4:  [('ArF immersion', 57.19), ('EUV NA 0.33', 16.36), ('High-NA 0.55', 9.82)]
ArF immersion: lambda/NA^2 = 105.9 nm
EUV NA 0.33: lambda/NA^2 = 124.0 nm
High-NA 0.55: lambda/NA^2 = 44.6 nm
NXE 13 nm ->  k1 = 0.318
EXE  8 nm ->  k1 = 0.326

Four things fall out of these numbers.

First, the wavelength does most of the work. At the same k1 of 0.30, 193 nm immersion resolves about 43 nm in a single exposure and 0.33 NA EUV resolves about 12 nm. The ratio is driven by 193 / 13.5, which is 14.3, partly offset by the much lower NA of EUV optics. This is the "more than 14 times shorter" figure ASML uses.

Second, ASML's published resolutions are not at the theoretical floor. The NXE product pages quote 13 nm at NA 0.33, and the EXE pages quote 8 nm at NA 0.55. Both imply a k1 of about 0.32, which is a production grade value with margin for process variation, not a laboratory best case.

Third, High-NA buys resolution in proportion to NA. 0.55 / 0.33 is 1.667, which is why ASML can say that the EXE prints features "1.7 times smaller". Density scales with the square of the linear shrink, and 1.7 squared is 2.89, which matches ASML's "transistor densities 2.9 times higher".

Fourth, depth of focus shrinks with the square of NA. The λ / NA² term falls from 124 nm at NA 0.33 to 44.6 nm at NA 0.55, a factor of 2.78. Real depth of focus depends on k2, the illumination, the feature type and the resist, so do not read 44.6 nm as a usable process window. The ratio is the point: High-NA has about a third of the focus budget of standard EUV for comparable features, which pushes resists thinner and makes wafer flatness and focus control harder.

Why not simply go to an even shorter wavelength? Because you need a source that is bright enough and optics that reflect it. At 13.5 nm, molybdenum and silicon multilayers reflect a useful fraction of the light at near normal incidence, and tin plasma emits strongly in a narrow band around that wavelength. The source and optics sections below show how tight that match is.

The light source: tin droplets, two laser pulses and a plasma

What ASML says

ASML's light and lasers page gives the clearest short description of the laser produced plasma (LPP) source: "molten tin droplets of around 25 microns in diameter are ejected from a generator at 70 meters per second. As they fall, the droplets are hit first by a low-intensity laser pulse that flattens them into a pancake shape. Then a more powerful laser pulse vaporizes the flattened droplet to create a plasma that emits EUV light." The process "is repeated 50,000 times every second".

The same page places EUV in the history of lithography light sources: mercury lamps at 436 nm (g-line) and 365 nm (i-line), then krypton fluoride excimer lasers at 248 nm, then argon fluoride excimer lasers at 193 nm, then EUV at 13.5 nm. Each step needed a new way to make light, but EUV was the biggest jump, from a gas discharge laser to a plasma.

Worked numbers on the droplet train

Two of ASML's numbers give a geometry check. A droplet moving at 70 m/s, with 50,000 droplets per second, has a spacing of 70 / 50,000 = 0.0014 m, or 1.4 mm, between droplets. That gap matters: the plasma from one droplet expands and must not disturb the next droplet before it is hit. The Fomenkov paper says the same thing in engineering terms, noting that "greater droplet-to-droplet separation is necessary for power scaling" and that higher velocity droplets help.

v = 70.0          # m/s, ASML
f = 50_000        # droplets per second, ASML
print("spacing:", v / f * 1000, "mm")        # 1.4 mm
print("time between droplets:", 1e6 / f, "us") # 20 us

Twenty microseconds between droplets is the window in which the laser timing system has to find the next droplet, fire the prepulse, wait for the pancake to form, and fire the main pulse.

The drive laser

The drive laser is a pulsed CO2 laser built by TRUMPF. TRUMPF's EUV drive laser page says the system takes a pulse of "a few watts" and "sequentially amplifies a laser pulse by more than 10,000 times", reaching "40 kilowatts of laser power", with "an extremely high peak output power in the MW range". A seed module with two seed lasers pre-amplifies to 100 W, a chain of resonators does the main amplification, and a beam transport system carries the beam "up to 30 meters" to the droplet chamber. TRUMPF also confirms the two pulse scheme: a low power prepulse hits the droplet first, then the main pulse follows.

The Fomenkov paper adds the laser wavelength: the "10.6-μm wavelength" beam is focused through a central aperture in the collector onto the droplet. It also shows that the prepulse is not cosmetic: prepulse shaped disk targets and lower density targets gave higher conversion efficiency and EUV power, and the authors report a mean conversion efficiency (CE) "in excess of 5%" on a modified NXE:3300B source and "CE of 6% and 375 W in-burst EUV power" in development labs.

The power budget

The 2017 paper is unusually direct about why the source must be so powerful. Its section on requirements says: "To achieve a throughput of 100 wafers per hour (WPH) at a typical scanner duty cycle of 60%, the power at the wafer should be greater than about 550 mW, which means that the EUV source power provided to the exposure tool at intermediate focus should be greater than 200 W." It adds that with an average conversion efficiency of about 5%, and after collection and gas transmission losses, "more than 20 kW of laser power is needed to produce 200 W of EUV power at the intermediate focus". For comparison, it says "current 193-nm light sources for lithography have power levels of 90 W to support a throughput of 200 WPH".

Here is that budget as a chain. The 5% and 20 kW come from the paper. The 1,000 W line is our arithmetic, and it is in band EUV emitted by the plasma in all directions, not light that reaches the scanner.

  >20,000 W   CO2 laser average power on target   (Fomenkov et al.)
     x 0.05   conversion efficiency into 2% band at 13.5 nm
  = 1,000 W   in-band EUV emitted by the plasma   (our arithmetic)
     x collection solid angle, collector reflectivity, gas transmission
  >  200 W    EUV at intermediate focus (IF)       (Fomenkov et al.)
     x about 2% for 10 mirror reflections at 67%
  ~ a few W   reaches the wafer plane (mirror losses only)
  > 550 mW    needed at the wafer for 100 WPH       (Fomenkov et al.)

The gap between "a few watts" after mirror losses and "more than 550 mW" in the paper's throughput model is real and is not an error. Mirror reflectivity is only one loss. The reticle's absorber blocks part of the light by design, the illumination pupil and slit clip part of it, and the paper's throughput model includes the duty cycle and other system losses that it does not break out line by line. We have not tried to reconstruct those other losses, because the paper does not publish them.

Spectral purity, etendue and dose control

The source has to do more than produce watts. The 2017 paper lists five requirements: power, spectral content, etendue, dose stability and lifetime.

• Spectral content. Because the scanner uses many Mo/Si mirrors, "the source spectrum needs to be centered at 13.5 nm within a bandwidth of 2%". The source also has to limit out of band light between 130 nm and 400 nm and infrared light from the drive laser, because those wavelengths can reach the resist or heat the optics.
• Etendue. The product of the plasma's emitting area and the collector's solid angle must stay within what the illuminator can accept; the paper gives the generally accepted specification as less than 1 to 3.3 mm2 sr, depending on the optical design. A plasma that is too large wastes light that the optics cannot use.
• Dose stability. Each point on the wafer receives light from many pulses as the slit scans over it, so pulse to pulse variations average out. Sources operating at 50 kHz "are capable of" less than 0.5% dose error, according to the paper.
• Lifetime. A target of 30,000 hours was set for the most critical source components, and the collector is "arguably the most critical component in terms of lifetime".

The collector mirror and debris mitigation

The collector sits right next to a plasma that is spraying tin ions, neutral atoms and fragments. It is an ellipsoidal, normal incidence multilayer mirror: the plasma sits at one focus and the intermediate focus, the hand-off point into the scanner, sits at the other. The 2017 paper shows a collector with a 5.5 sr collecting angle, and notes that only about a 2π sr hemisphere of the plasma's 4π sr emission is usable in practice. As a quick check, 5.5 sr is 5.5 / (4π), which is 43.8% of the full sphere.

Keeping that mirror clean is the central engineering problem of the source. The paper describes three tools:

1. Hydrogen buffer gas. "Debris mitigation in the source relies on using hydrogen as a buffer gas." The gas slows down high energy ions before they reach the collector and cools the region near the plasma.
2. Capping layers. Special protective layers on top of the multilayer coating resist damage.
3. Hydrogen radical cleaning. "A tin cleaning technique using hydrogen radicals was developed to enhance the rate of tin removal from the collector."

With those measures the paper reports a demonstrated collector lifetime of "over 100 Billion pulses". At 50,000 pulses per second, 100 billion pulses is 2,000,000 seconds of firing, about 556 hours, or a little over 23 days of continuous operation. That is the 2017 demonstrated figure, not a current specification, and we could not find a current collector lifetime published by ASML.

pulses = 100e9
rate = 50_000
hours = pulses / rate / 3600
print(round(hours, 1), "hours;", round(hours / 24, 1), "days")  # 555.6 hours; 23.1 days

The optics: multilayer mirrors in vacuum

Why there are no lenses

ASML's lenses and mirrors page puts it simply: "there are no lenses for EUV lithography. Since most materials absorb EUV light, the lenses would absorb the light in the system." Instead, EUV scanners use "ultrasmooth, multilayer mirrors inside a vacuum chamber". Each mirror "has over 100 layers of materials", and the mirrors "are polished to a smoothness of less than one atom's thickness". ASML's analogy: if the mirrors were the size of Germany, the tallest bump would be about a millimetre high. On the same page ASML says its largest EUV mirrors "are 1 meter across and smooth down to tens of picometers".

How a Mo/Si multilayer reflects

A single interface between two materials reflects only a tiny fraction of EUV light at near normal incidence, because the refractive indices of all materials are very close to 1 at 13.5 nm. A multilayer mirror stacks many alternating layers of a heavier absorber (molybdenum) and a lighter spacer (silicon), with each molybdenum and silicon pair about half a wavelength thick. The small reflections from each interface then add in phase, the same principle as a Bragg reflector. More than 100 layers in total means dozens of Mo/Si pairs.

That design has two consequences:

• The reflectivity is high but not very high. The 2017 source paper says "EUV mirrors typically have a reflectivity of less than 70%". Every mirror throws away about a third of the light that hits it, mostly as heat.
• The reflection band is narrow. A multilayer only reflects well near its design wavelength and angle range, which is why the source has to put its energy inside a 2% band around 13.5 nm, and why the angles of light at the mask matter so much for High-NA.

What the mirror train costs you

The 2017 paper gives a worked example: "in the scanner with 10 reflections from intermediate focus (IF) to the wafer and peak mirror reflectivity of 67%, the overall transmission is about 2%." Here is the arithmetic, plus a few variations to show how sensitive throughput is to mirror quality. The mirror counts other than 10 are illustrative, not published tool configurations.

for R, n in ((0.67, 10), (0.70, 10), (0.70, 6), (0.70, 11)):
    print(f"R={R:.2f}, {n} reflections: {R**n*100:.2f}% transmitted")

R=0.67, 10 reflections: 1.82% transmitted
R=0.70, 10 reflections: 2.82% transmitted
R=0.70, 6 reflections: 11.76% transmitted
R=0.70, 11 reflections: 1.98% transmitted

Two lessons. A three point gain in reflectivity per mirror, from 67% to 70%, raises total transmission from 1.82% to 2.82%, a 55% relative improvement in light at the wafer. And each extra mirror costs about 30% of whatever light is left. Optical designers trade every mirror they add for a better corrected image or a wider field against throughput.

Run the same chain against a source delivering 250 W at intermediate focus and the 10 mirror, 67% case leaves about 4.6 W after mirror losses alone. That is before the reticle absorber and pupil clipping, and before the duty cycle.

Mirror heating and active correction

Light that is not reflected is absorbed, so each mirror heats up during exposure. ASML says repeated intense pulses "cause the optical system to warm up, which leads to distortions", measured "in millikelvins and nanometers", and that "thousands of actuators allow the exact position and orientation of individual lens and mirror elements to be minutely adjusted". For the NXE:3800E specifically, ASML says that "by mitigating mirror heating, the system is able to offer imaging with reduced aberrations and increased stability". ASML has not published how many actuators are in a given EUV tool or the thermal budget per mirror, so we do not quote one.

The scale of the optics

ZEISS SMT builds the illumination and projection optics. Its January 2024 article on High-NA gives some of the few hard numbers available on the optical system itself:

• The High-NA projection optics consist of "over 40,000 parts" and weigh "approximately twelve tons".
• The High-NA illumination system "weighs more than six tons and consists of more than 25,000 parts".
• The High-NA optics are "about seven times larger in volume and weight" than the optics in current EUV tools.
• The individual High-NA mirrors weigh "several hundred kilograms", which ZEISS says makes them "about twice as large and ten times as heavy as current EUV mirrors".
• To measure those mirrors, ZEISS built a vacuum metrology chamber of five by ten metres with "more than a hundred thousand parts" and a total weight of "more than 150 tons".

The reticle: a mirror with a pattern on it

Reflective masks

In DUV lithography the mask (reticle) is a quartz plate with a chrome or similar pattern, and light passes through it. In EUV, quartz would absorb the light, so the reticle is itself a multilayer mirror. ASML describes EUV reticles as "multilayer reflectors that use interference to reflect light from the pattern". An absorber layer patterned on top of the multilayer defines the dark areas.

Because the mask is reflective, light has to arrive at an angle. If it came in perpendicular, the reflected light would go straight back into the illuminator. That oblique angle has side effects. The absorber has a real thickness, so it casts shadows that depend on the orientation of the feature. Lines that run one way print slightly differently from lines that run the other way, and the best focus can shift between features. Lithographers group these as mask 3D effects. Optical proximity correction (OPC), which ASML describes as adjusting the mask pattern to compensate for how light diffracts, is used to correct for them alongside illumination optimisation.

Reduction ratio and the mask size

The projection optics shrink the reticle pattern by four times in standard EUV, according to ASML. With a full EUV exposure field of 26 mm by 33 mm at the wafer, the patterned area on the mask is 104 mm by 132 mm, which fits on the industry standard six-inch (about 152 mm) square mask blank. That fit is not an accident; it is the reason the industry protected 4x reduction for so long, and as we will see, it is why High-NA ended up anamorphic.

fx, fy = 26, 33        # mm at the wafer, full field
print("on mask at 4x:", fx*4, "x", fy*4, "mm")   # 104 x 132 mm
print("six-inch blank is about", round(6*25.4, 1), "mm square")  # 152.4 mm

The pellicle

A pellicle is a thin membrane stretched over a frame a short distance above the mask surface. Any particle that lands on it is out of focus at the wafer, so it does not print. In DUV, pellicles are standard. In EUV they are hard, because the membrane has to be thin enough to transmit EUV twice (once in, once out after reflection), strong enough to survive the scanner's vacuum pump-down, and able to withstand intense EUV heating.

The figures available from primary sources are from the pellicle makers and research institutes. In December 2023, imec and Mitsui Chemicals announced a partnership to commercialise carbon nanotube (CNT) pellicles, saying the CNT pellicles have "extremely high EUV transmittance" of at least 94%, "very low EUV reflectance", and the ability "to withstand EUV power levels beyond 1kW, thereby supporting the future EUV source roadmap" above 600 W. The partners targeted introduction "in high-power EUV systems in the 2025-2026 timeframe". Whether a given fab uses a pellicle on a given layer is a process decision that the fabs do not publish.

Because light passes through the pellicle twice, its single pass transmission is squared in the light budget. A 94% pellicle passes 0.94 × 0.94, or 88.4%, of the light. A 90% pellicle passes 81%. That is a 7 point difference in light at the wafer from one very thin membrane.

for t in (0.90, 0.94, 0.97):
    print(f"single pass {t:.0%} -> double pass {t*t:.1%}")
# single pass 90% -> double pass 81.0%
# single pass 94% -> double pass 88.4%
# single pass 97% -> double pass 94.1%

Vacuum, hydrogen and contamination control

ASML is blunt about why the tool is a vacuum machine: "EUV light is absorbed by everything, even air. So the whole light path and everything the light interacts with, from source to wafer, must be in high vacuum." The source vessel adds a controlled hydrogen atmosphere for debris mitigation, and the rest of the optical path must be kept free of contaminants that would deposit on mirrors under EUV exposure.

This has practical consequences that do not exist in DUV:

• Every wafer goes through a load lock. The wafer handler moves wafers "in and out of the system's vacuum environment through an air lock", with a positioning accuracy of 25 µm and a surface temperature uniform to within 2 mK, per ASML.
• Thermal control is harder. In vacuum there is no air to carry heat away by convection, so heat from absorbed light has to be removed by conduction and active cooling.
• Materials are restricted. Anything inside the vacuum that outgasses can deposit on optics. The details of material qualification are proprietary.

Stages and mechatronics: nanometres at fighter-jet accelerations

Step and scan, in one paragraph

An EUV scanner does not expose the whole field at once. The illuminator forms a narrow, curved slit of light on the reticle. During each exposure the reticle moves through that slit while the wafer moves the other way beneath the projection optics, so the pattern is painted across the field like a photocopier. Then the wafer steps to the next field and the scan repeats. ASML describes it this way: "the reticle moves smoothly through a narrow slit of light, exposing only a small part of the pattern at a time. Meanwhile, the wafer moves smoothly in the opposite direction to capture the whole pattern."

Published stage figures

ASML's mechanics and mechatronics page and its EUV product page give the following numbers. Some are generic to ASML scanners rather than specific to EUV, and we mark which.

A quick check on the reticle stage figure: 150 / 9.80665 is 15.3, so 150 m/s2 is indeed about 15 g. ASML's comparison, a car going from 0 to 100 km/h "in just 0.1 seconds", is generous: at a constant 150 m/s2, 100 km/h (27.8 m/s) takes 27.8 / 150 = 0.185 seconds. The underlying acceleration figure is the one to use.

Why the reticle stage works harder than the wafer stage

Because the optics reduce the image four times, the reticle must travel four times as far and four times as fast as the wafer during each scan, and it must reverse direction just as often. ASML describes synchronising wafer and reticle "to the nanometer and nanosecond as they accelerate at 5 g and 15 g in opposite directions". The higher reticle acceleration is the 4x reduction showing up in the mechanics.

In High-NA, the 8x reduction in the scan direction means the reticle has to move eight times as far as the wafer in that direction. ASML says the EXE:5000 "has new, faster wafer and reticle stages to achieve the highest productivity". ASML has not published the EXE stage accelerations on its product pages.

Dual stages: measure one wafer while exposing another

The TWINSCAN idea is that the stage system carries two wafer tables. "While one wafer is being exposed, the position of the other wafer is measured by the machine's metrology sensors." The measurement side maps the wafer's height (for focus) and the positions of alignment marks (for overlay), so that when the wafer swaps over to the exposure side the scanner already knows how to correct each field. ASML's NXE:3800E page says the tool "optimizes imaging and overlay performance for each exposed wafer by combining in-situ measurements with per-wafer correction capability of the optics and stages". The NXE:3800E also uses a new bottom module, shared with the EXE platform, with "a new wafer handler, faster wafer stages and other components needed to support increased throughput".

Overlay and metrology

What overlay is

Overlay is the accuracy with which one patterned layer lines up with the layers beneath it. ZEISS says the exposure process is repeated up to 100 times to build up a chip's three dimensional structures, and every one of those layers has to register to the ones it connects to. ASML's own definition on its measuring accuracy page: overlay is "the accuracy with which two layers of a chip are aligned".

Overlay errors come from many places: the stages, the wafer's distortion from previous process steps, heating of the reticle and optics, lens or mirror aberrations, and differences between scanners (which matters when one layer is printed on a DUV tool and the next on an EUV tool).

How it is measured and corrected

ASML describes two kinds of external metrology:

• Diffraction based optical metrology. Its YieldStar systems shine light on repeating metrology targets on the wafer and read the diffracted pattern with a camera. The shape of the target changes how it diffracts, so overlay and focus can be inferred. These tools "are usually integrated into the production line" and loop data "back to the lithography system for real-time corrections".
• E-beam metrology and inspection. Electron beam tools resolve about 1 nm, which ASML says is enough to "spot those tiny misprints", but they are slower, so they are typically used after etch and on samples.

Inside the scanner, alignment sensors on the measurement side of the TWINSCAN stage read marks on each wafer, and level sensors map its height.

What has not been published

ASML's current EUV product pages describe overlay "improvements" for the NXE:3800E and the EXE:5200B but do not list numeric overlay specifications. Older product sheets and conference papers have quoted figures for specific tools under specific conditions (for example "matched machine" overlay between two tools, or "dedicated chuck" overlay on one wafer table). We have not reproduced any such figure here because the current pages do not state one, and overlay numbers only mean something alongside their exact measurement conditions.

Throughput: what "wafers per hour" means

ASML's EUV product pages give throughput as a minimum, at a stated dose. Here are the figures we read from those pages in October 2026:

These are peak, specified figures, not sustained fab output. A fab's real output depends on the layers being exposed, the dose each layer needs, the number of fields per wafer, tool availability, maintenance and reticle changes. We found no primary source for sustained figures on named products, and we do not estimate them.

Translating the numbers

for name, wph in (("NXE:3800E", 220), ("EXE:5200B", 175), ("EXE:5000", 110)):
    print(f"{name}: {3600/wph:.2f} s per wafer")

NXE:3800E: 16.36 s per wafer
EXE:5200B: 20.57 s per wafer
EXE:5000: 32.73 s per wafer

In about 16 seconds the NXE:3800E has to swap a wafer in and out through vacuum, and expose every field. ASML's mechanics page speaks of printing "almost 100 different places" on a wafer. That leaves a fraction of a second per field, including the scan, the step to the next field, and the stage settling.

Why dose matters so much

Throughput depends directly on dose. The source makes a fixed number of photons per second. A resist that needs 50 mJ/cm2 needs two thirds more light per field than one that needs 30 mJ/cm2, so, when the tool is light limited, each field takes longer. That is why ASML quotes throughput at a stated dose, and why the Fomenkov paper's throughput model is expressed partly in terms of source power per unit of resist sensitivity. It also sets up the central tension of EUV: lower dose means higher throughput but, as the next section shows, more random variation.

ASML says the 40% higher imaging contrast of its 0.55 NA systems "allows chipmakers to reduce the amount of light per exposure, or dose", which helps throughput. The EXE:5200B gets its higher throughput from "an improved EUV light source" that delivers "increased power at the wafer level".

Stochastic defects and the resist

Counting photons

Each 13.5 nm photon carries far more energy than a 193 nm photon, so the same dose contains far fewer photons. Photon energy is E = hc / λ. Here is the calculation, using exact SI values for h, c and the electron charge.

import math
h = 6.62607015e-34      # J s (exact, SI)
c = 299_792_458         # m/s (exact, SI)
e = 1.602176634e-19     # C (exact, SI)

def photon(lam_nm):
    return h * c / (lam_nm * 1e-9)

print("EUV photon:", round(photon(13.5) / e, 2), "eV")   # 91.84 eV
print("ArF photon:", round(photon(193) / e, 2), "eV")    # 6.42 eV

for dose in (30, 50):                    # mJ/cm2
    J_per_nm2 = dose * 1e-3 / 1e14       # 1 cm2 = 1e14 nm2
    n = J_per_nm2 / photon(13.5)
    N = n * 100                          # photons into a 10 nm x 10 nm square
    print(f"{dose} mJ/cm2: {n:.1f} photons/nm2, "
          f"{N:.0f} per 100 nm2, shot noise {100/math.sqrt(N):.2f}%")

print("ArF at 30 mJ/cm2:", round(30e-3/1e14/photon(193), 1), "photons/nm2")

EUV photon: 91.84 eV
ArF photon: 6.42 eV
30 mJ/cm2: 20.4 photons/nm2, 2039 per 100 nm2, shot noise 2.21%
50 mJ/cm2: 34.0 photons/nm2, 3398 per 100 nm2, shot noise 1.72%
ArF at 30 mJ/cm2: 291.5 photons/nm2

These are incident photons. Only a fraction is absorbed in a thin resist film, and the number of chemical events per absorbed photon depends on the resist, so the real statistics are worse than this simple count suggests. The point of the calculation is the comparison: at the same dose, a 193 nm exposure delivers about 14 times as many photons as an EUV exposure. Photon arrival is a Poisson process, so the relative fluctuation scales as one over the square root of the count. Fewer photons means larger random variation in how much energy each tiny region receives.

From photon noise to printing failures

Those fluctuations turn into three kinds of problems, all lumped together as stochastic effects:

• Line edge and line width roughness. Edges of lines are not straight at the nanometre scale.
• Local critical dimension uniformity. Identical features printed next to each other come out with slightly different sizes.
• Printing failures. Occasionally a contact hole does not open (a missing contact), or two lines bridge, or a line breaks. These are rare per feature, but a chip has billions of features.

The imec paper by Peter De Bisschop in the Journal of Micro/Nanolithography, MEMS, and MOEMS (December 2017) is a standard reference here. It argues that the usual roughness and local CD uniformity metrics are not enough on their own, and introduces algorithms that count stochastic printing failures in SEM images of line and space and contact arrays, as a complementary "NOK" (not OK) metric. It also explores simple predictors of CD variability and failure that could be calibrated and added to OPC verification.

The practical trade-off is the triangle that resist engineers talk about: resolution, line roughness and sensitivity (dose). Push one corner and the others suffer. Lower dose raises throughput but raises stochastic variation. Smaller features make each feature contain fewer photons and fewer resist molecules. Higher dose fixes noise but costs throughput, and as the throughput section showed, it costs it directly. High-NA helps a little here because its higher contrast gives a sharper aerial image for the same feature, which ASML says "reduces the number of patterned defects".

We have not quoted any specific resist's sensitivity or defect rate, because we could not tie one to a primary source with its full test conditions.

High-NA EUV: anamorphic optics and half fields

Why not just raise the NA at 4x?

Raising NA from 0.33 to 0.55 means the light cone at the wafer gets wider. With 4x reduction, the light cone at the mask also gets wider. The SPIE Newsroom article by Jan van Schoot and Kars Troost of ASML and Sascha Migura and Bernhard Kneer of ZEISS (12 January 2016) explains the problem: at 4x, the wider cone at the mask means the light going in and the light coming out of the reflective mask start to overlap, and if you tilt the beam further to separate them, shadowing from the absorber increases and contrast drops. The authors state that reducing the angular range at the mask by increasing magnification is "the only solution to the shadowing problem".

Isomorphic 8x versus anamorphic 4x/8x

The obvious fix, 8x reduction in both directions, halves the angles at the mask. But it also quarters the field. With a six-inch mask, an isomorphic 8x system would give a 13 mm by 16.5 mm field, and the article says such a system would reach "less than 100 wafers per hour", which the authors judged uneconomic.

The anamorphic answer is to use different reduction in each direction: 4x across the slit (the x direction) and 8x along the scan (the y direction). The authors put the 8x in the scan direction, where it deals with the shadowing problem, while 4x across the slit keeps the full 26 mm width. The result is a 26 mm by 16.5 mm field, half the standard full field and twice the isomorphic 8x field. The article says the design targets "more than 150 wafers per hour". ASML's EXE:5000 page describes the same choice: "These so-called anamorphic optics provide the best imaging while allowing chipmakers to continue using traditionally sized reticles."

             Standard EUV (4x / 4x)          High-NA EUV (4x / 8x)
 On mask:    104 mm x 132 mm                 104 mm x 132 mm
 At wafer:    26 mm x 33 mm  (858 mm2)        26 mm x 16.5 mm (429 mm2)
 Scan (y):   4x reduction                    8x reduction
 Slit (x):   4x reduction                    4x reduction

print("full field:", 26*33, "mm2; half field:", 26*16.5, "mm2")
print("on mask at 4x/8x:", 26*4, "x", 16.5*8, "mm")    # 104 x 132 mm

The anamorphic choice has a cost in the mask itself: features on a High-NA mask are drawn stretched twice as long in the scan direction as the wafer feature, so mask data preparation, OPC and inspection all need to handle non-square magnification.

Half fields and stitching

A half field changes how chips are laid out. A die that fits in a 26 mm by 33 mm field on standard EUV may not fit in 26 mm by 16.5 mm. Large dies then need in-die stitching: printing one half of the die in one exposure and the other half in the next, with the boundary placed where the pattern can tolerate it. This follows directly from the geometry: any die taller than 16.5 mm in the scan direction cannot be printed in one High-NA exposure. Large AI accelerators and GPU dies, which already push the full field, are the obvious case; for how those large dies are built and packaged, see our post on how a GPU is made, from wafer to HBM package.

A half field also doubles the number of exposures per wafer. A simple grid estimate, placing fields on a 300 mm wafer with a 3 mm edge exclusion and counting only fields that fit entirely, gives 64 full fields against 132 half fields:

import math
R = 150 - 3   # usable radius, mm (3 mm edge exclusion, our assumption)
def fields(fx, fy):
    n = 0
    for i in range(-15, 15):
        for j in range(-15, 15):
            x0, y0 = i * fx, j * fy
            corners = [(x0, y0), (x0+fx, y0), (x0, y0+fy), (x0+fx, y0+fy)]
            if all(math.hypot(x, y) <= R for x, y in corners):
                n += 1
    return n
print(fields(26, 33), fields(26, 16.5))   # 64 132

This is a rough estimate with one grid placement, not a fab layout (real layouts shift the grid and include partial fields at the edge), but it shows why High-NA needed faster stages. Twice the fields means twice the stepping and turnarounds per wafer.

The published High-NA numbers

Where High-NA is in deployment

ASML's EUV page says the EXE platform "will support high-volume chip manufacturing in 2025 to 2026". ZEISS wrote in January 2024 that the first High-NA systems "are scheduled to start series production in 2026". ASML's 2024 results presentation says the company "shipped and recognized revenue from multiple EXE:5000 systems and NXE:3800 systems" in 2024. ASML describes the EXE:5200B as "the second 0.55 NA" system. Which fabs use High-NA on which layers, and from when, is a matter for those companies' own disclosures, and we do not speculate here.

DUV, EUV and High-NA side by side

The DUV column is here for comparison only. For where lithography sits in the full chip making flow, see our post on how semiconductors are made from sand to chip, and for what the chips printed this way are used for, see AI chip architecture.

The supply chain behind one machine

An EUV scanner is the product of a supply chain, not one company. The pieces named in primary sources:

• ASML designs and integrates the system, and makes the source after acquiring Cymer, which its EUV page describes as "a company specialized in light source technology", to "accelerate EUV source development". ASML's EUV page says the technology "took more than two decades to develop".
• ZEISS SMT makes the illumination and projection optics. ASML says all its lithography systems have used ZEISS optics "since the late 1980s". ZEISS says about 2,000 of its more than 9,349 SMT employees (full time equivalent, 2025) work on High-NA, and that its network includes "around 1,200 national and international companies".
• TRUMPF makes the CO2 drive laser, per its own product page.
• Pellicle and mask suppliers, including the CNT pellicle work of imec and Mitsui Chemicals, supply the mask side.
• imec, the Leuven research institute that received one of the first EUV demo tools in 2006, works with suppliers on pellicles and other parts of the patterning ecosystem.

Cost and size

ASML does not publish list prices. Its results presentation for 2024 says "EUV system sales reduced 9% to €8.3 billion, recognized revenue on 44 EUV systems (NXE & EXE)". Dividing gives an average of about 188.6 million euros per recognised EUV system in 2024. That average mixes NXE and EXE tools and reflects revenue recognition timing, so it is not the price of any one tool; press estimates for individual High-NA systems are higher, but they are estimates, and we do not repeat them as facts.

print(round(8.3e9 / 44 / 1e6, 1), "million euros average per recognised EUV system, 2024")

On size, the primary sources give component level figures rather than a footprint: TRUMPF's beam transport runs "up to 30 meters" from laser to source chamber, and ZEISS's High-NA projection optics alone weigh about 12 tonnes, with the illumination system adding more than 6 tonnes. ASML has not published a single overall footprint or shipping weight on the pages we checked.

Export controls, stated neutrally

Lithography tools are subject to export controls. We describe only what official sources say.

The Netherlands. The Dutch government introduced a national export authorisation requirement for certain advanced semiconductor manufacturing equipment, in force since 1 September 2023. On 7 September 2024 the measure was expanded to "more types of equipment". The government says it "will assess applications on a case-by-case basis, so this is not an export ban", and that the measure "applies to exports from the Netherlands to destinations outside the EU". On 15 January 2025 the minister announced a further modification effective 1 April 2025, covering, for example, "specific measuring and inspection equipment". That announcement says the national measure had until then covered "a number of very specific technologies in the production cycle of semiconductors, such as lithography equipment".

The United States. On 2 December 2024 the Bureau of Industry and Security announced rules adding controls on 24 types of semiconductor manufacturing equipment and 3 types of software tools, covering "certain etch, deposition, lithography, ion implantation, annealing, metrology and inspection, and cleaning tools", added 140 entities to the Entity List, and created two new foreign direct product rules for semiconductor manufacturing equipment. We do not characterise the policy merits, and the rules change; check the official pages before relying on any of this.

Common mistakes

1. Treating 13 nm or 8 nm as a "node". The resolution figures on ASML's pages are printable feature sizes for a single exposure. ASML's own pages use node names separately (the NXE:3800E supports "2 nm Logic nodes" while printing 13 nm features), so the two are not the same measurement.
2. Using k1 = 0.25 numbers as real capability. The Rayleigh floor gives 10.2 nm at NA 0.33 and 6.1 nm at NA 0.55. Production values sit around k1 0.32 by ASML's own quoted resolutions.
3. Quoting throughput without the dose. "220 wafers per hour" is only meaningful at the 30 mJ/cm2 stated next to it. At higher doses the same tool is slower.
4. Confusing source power with power at the wafer. Hundreds of watts at intermediate focus become a few watts or less at the wafer after mirrors, mask and pupil losses.
5. Assuming more NA is free. Depth of focus scales with 1 / NA², so High-NA has roughly a third of the focus scaling term of standard EUV, plus a half field and stitching.
6. Ignoring stochastics. At 30 mJ/cm2 there are about 20 incident EUV photons per square nanometre. Defects that are random, rare and per feature dominate the yield discussion at the smallest pitches.
7. Treating a pellicle's transmission as single pass. Light crosses the pellicle twice. 90% single pass is 81% in the budget.
8. Repeating unsourced prices. Tool prices circulate widely without primary sources. ASML does not publish list prices.
9. Forgetting the software. The tool's control and metrology software is part of the fab's attack surface and supply chain, and needs an inventory like any other software.

FAQ

How does an EUV lithography machine make light?

It fires a pulsed CO2 laser at molten tin droplets about 25 microns across, falling at 70 m/s, 50,000 times per second. A low intensity prepulse flattens each droplet into a pancake, and a powerful main pulse turns it into a plasma that emits 13.5 nm light, according to ASML. A multilayer collector mirror gathers that light and focuses it into the scanner.

Why does EUV lithography use mirrors instead of lenses?

Almost every material absorbs 13.5 nm light, including glass and air. ASML says "there are no lenses for EUV lithography". The optics are multilayer mirrors with more than 100 alternating layers, and the whole light path is in high vacuum.

What is the reflectivity of an EUV mirror?

A peer reviewed source paper from Cymer and ASML says EUV mirrors "typically have a reflectivity of less than 70%". Its worked example of 10 reflections at 67% gives about 2% overall transmission from intermediate focus to the wafer.

What is the resolution of EUV and High-NA EUV?

ASML quotes 13 nm for its 0.33 NA NXE systems and 8 nm for its 0.55 NA EXE systems. Using the Rayleigh criterion, both correspond to a k1 factor of about 0.32.

What does anamorphic mean in High-NA EUV?

The projection optics demagnify by different amounts in the two directions: 4x across the slit and 8x along the scan. This keeps light angles at the mask small enough to avoid excessive shadowing while still using standard six-inch masks. The cost is a half-size exposure field of 26 mm by 16.5 mm.

How many wafers per hour can an EUV scanner expose?

ASML lists at least 220 wafers per hour at 30 mJ/cm2 for the NXE:3800E, at least 110 for the EXE:5000 and at least 175 for the EXE:5200B, both at 50 mJ/cm2. These are specified peak figures, not sustained fab output.

What are stochastic defects in EUV lithography?

Random variations caused by the small number of photons and resist molecules per feature. At 30 mJ/cm2, EUV delivers about 20 incident photons per square nanometre, against about 290 for 193 nm light. The result is line roughness, size variation between identical features, and rare printing failures such as missing contacts.

How much does an EUV machine cost?

ASML does not publish list prices. Its 2024 results report 8.3 billion euros of EUV system sales on 44 recognised systems, which averages about 189 million euros per system across NXE and EXE tools. That is an average, not a price.

Who makes the parts of an EUV machine?

ASML designs and integrates the scanner and builds the light source (it acquired Cymer). ZEISS SMT makes the illumination and projection optics, and TRUMPF makes the CO2 drive laser. Mask, pellicle and resist suppliers and research hubs such as imec complete the ecosystem.

Are EUV machines subject to export controls?

Yes. The Netherlands has had a national authorisation requirement for certain advanced semiconductor manufacturing equipment since 1 September 2023, expanded in September 2024 and April 2025. The US Bureau of Industry and Security added controls on 24 types of semiconductor manufacturing equipment, including lithography tools, in December 2024.

Where Safeguard fits: the software inside the machine

Here is the honest bridge to Safeguard, and it is narrow.

A modern scanner is a large computer system as well as an optical one. It runs control software for the source, the stages and the optics; recipe and job management; metrology and correction loops that feed data back from tools like YieldStar; equipment interfaces to the fab's host systems; and service and diagnostic tools. Around the scanner sit computational lithography software for OPC and mask preparation, and the fab's own manufacturing execution systems. All of that software is built from components, including open source components, and those components get vulnerabilities and patches like any other software. We wrote about this in more depth in semiconductor fab SBOMs for machines and firmware.

What Safeguard can and cannot do here:

• Safeguard generates and analyses SBOMs in SPDX and CycloneDX formats and matches components against vulnerability data enriched with EPSS and CISA KEV. If a tool vendor provides an SBOM for its software, or a fab builds its own integration code and containers, Safeguard can scan that and show which projects contain a given component and version.
• Safeguard's Third-Party Risk Manager can request SBOMs from vendors and track supplier risk, which fits the way fabs depend on tool vendors for embedded software.
• Safeguard deploys as SaaS, in a private VPC, on premises or fully air-gapped, which matters for networks that cannot reach the internet.
• Safeguard does not analyse lithography hardware, does not scan firmware images, does not generate hardware bills of materials, and does not touch tool control systems. A fab's control over the software inside a vendor's tool depends on what the vendor provides and supports.

A lithography tool's optics never get a CVE, but the software around it does: control and metrology stacks, equipment interfaces, OPC and mask tooling, and the fab's own integration code all carry open source components. The fit for Safeguard here is indirect and limited to software you build or can get an SBOM for, but that software still needs the same patch discipline as anything else.

More in this series

Other posts in our GPUs, CPUs, QPUs and lithography series:

• AMD GPU Architecture Explained: GCN, RDNA, CDNA, Infinity Fabric and HIP
• CPU vs GPU vs QPU Explained: How Each Works and Why They Coexist
• CUDA Programming Model Explained: Grids, Blocks, Warps and Memory
• GPU Memory and Interconnects: HBM, GDDR, NVLink, PCIe, CXL
• CUDA vs HIP vs SYCL vs OpenCL vs Metal vs Vulkan vs Triton Compared
• GPU Software Supply Chain: Drivers, CUDA, cuDNN, NCCL and Your SBOM
• How a QPU Works: Qubit Chips, Fridges, Control Pulses and Readout
• How CPUs Work: Pipelines, Out-of-Order, Caches, Branches, SIMD
• How GPUs Work: Graphics Pipeline, Shader Cores, Ray Tracing and Compute
• Inside an NVIDIA SM: Warp Schedulers, Registers, Tensor Cores
• Intel GPU Architecture: Xe Cores, XMX, Ponte Vecchio and oneAPI SYCL
• NVIDIA GPU Architecture History: From Tesla and Fermi to Blackwell
• NVIDIA vs AMD vs Intel vs Apple GPUs: Architectures Compared
• Optimizing a CUDA Matrix Multiply Step by Step, From Naive to Tensor Cores
• Photolithography Explained: Contact Printing to DUV Immersion and Overlay
• Tile-Based GPUs Explained: Apple, Mali, Adreno, PowerVR and TBDR

Fix it without waiting for upstream

Whatever the vulnerability, most of the risk sits in two gaps. The first is the time between a fix being published and that fix actually running in your production builds. The second, and worse, is the time before any fix exists at all, while a maintainer works out a patch and a release schedule. Waiting through both gaps is a habit, not a requirement. Safeguard gives teams three ways to close them.

1. Autonomous remediation: pull requests, not tickets

When a fixed version exists, Safeguard's Griffin models open a tested, policy gated pull request that moves the affected dependency to the safe version. You can run it on one repository or in bulk across every project that carries the vulnerable version. Remediation covers eight categories, including dependencies, licenses, security posture and findings. Reachability analysis ranks the vulnerable code paths your application actually calls first, so the first pull requests you merge are the ones that matter most. Autonomous remediation ships switched off, with every category set to Manual, so your team decides how much runs on its own and what still needs a human approval.

2. Gold Open Source: the safe version in seconds, free

gold.safeguard.sh is free and needs no login. Search any CVE or package to see affected and fixed versions, CVSS, EPSS, CISA KEV status and a recommended safe version, or use the "Am I affected?" checker. The same data is available through a free read API, README status badges and RSS threat feeds. The safeguard-sh/gold-scan-action GitHub Action can fail a build on a known exploited vulnerability, on any known vulnerability, or never, so a version you have just removed cannot quietly come back in next week's merge.

3. Gold Registry: start from components that are already fixed

registry.safeguard.sh provides hardened, drop in replacements for upstream packages and container images. Every Gold artifact is held continuously to zero exploitable critical or high CVEs, zero malware and a completed license check, with SLSA L3 or higher provenance, a Sigstore signature and a public evidence page you can hand to an auditor. An artifact loses its Gold badge if it regresses. Teams can point their own package directory at the registry so hardened equivalents resolve without changing how developers install anything.

When upstream has no fix yet, or will not ship one, Safeguard first works to get the fix accepted upstream. If the issue is severe or upstream will not move, Safeguard builds a fork, fixes the vulnerability there and publishes a hardened Gold build, so you are not stuck on a maintainer's release schedule. You can also request a hardened, compatibility tested build of a specific package. This fork and patch flow is in early access today, so ask which packages it covers before you plan around it.

One honest limit: when the vulnerable code lives in a vendor appliance, a hosted service or an operating system runtime you do not build yourself, the fix still has to come from that vendor or distribution. The steps above apply to the open source dependencies and container images you build and ship, which is where most teams carry the largest and least tracked share of their exposure.

See how Safeguard would help

The first demo sets up the local runner on your own machine, approves it with its device code, then scans from the terminal. Fab and equipment engineering networks are often isolated, and this shows how scans can run on a machine inside your own network, close to the integration code and containers you build.

Click through it at your own pace, or open it full screen.

The second demo is a real Safeguard CLI session. You install it, run safeguard to open the interactive terminal and ask it to fix the lodash CVE in a repository. It reads the finding and advisory, asks before any command that changes something, edits package.json to lodash 4.17.21, runs npm install and npm test with your approval, prints a summary and pushes nothing. The same flow applies to the dashboards, data pipelines and tool integration services that fab software teams write around their equipment.

Click through it at your own pace, or open it full screen.

The third demo connects Claude to the Safeguard MCP server with OAuth and shows how you choose which tools Claude can use. Once connected, you can ask which of your projects contain a component named in a new advisory, which is the first question to answer when a library used across equipment integration code turns out to be vulnerable.

Click through it at your own pace, or open it full screen.

To try it on your own projects, download Safeguard or read the CLI documentation.

Quick check

Sources

• ASML: EUV lithography systems
• ASML: TWINSCAN NXE:3800E
• ASML: TWINSCAN EXE:5000
• ASML: TWINSCAN EXE:5200B
• ASML: Light and lasers
• ASML: Lenses and mirrors
• ASML: Mechanics and mechatronics
• ASML: Measuring accuracy
• ASML: Pushing k1 further
• ASML Q4 and full year 2024 results presentation (Form 6-K, SEC)
• ZEISS SMT Magazine: High-NA-EUV lithography, mirroring the future (25 January 2024)
• TRUMPF: EUV drive laser
• Fomenkov et al., Light sources for high-volume manufacturing EUV lithography: technology, performance, and power scaling, Advanced Optical Technologies 6(3-4), 2017, doi:10.1515/aot-2017-0029
• van Schoot, Troost, Migura, Kneer, Improving the resolution of extreme-UV lithography scanners, SPIE Newsroom, 12 January 2016
• De Bisschop, Stochastic effects in EUV lithography: random, local CD variability, and printing failures, JM3 16(4) 041013, 2017
• Mitsui Chemicals and imec: strategic partnership to commercialize CNT pellicles for EUV (14 December 2023)
• Government of the Netherlands: export control measure for advanced semiconductor manufacturing equipment expanded (6 September 2024)
• Government of the Netherlands: export controls to be tightened from 1 April 2025 (15 January 2025)
• US Bureau of Industry and Security: Commerce strengthens export controls (2 December 2024)
• NIST: CODATA values of the fundamental physical constants

Last reviewed: 25 October 2026. Specifications are as published on the vendors' pages on that date; check them before relying on any figure.