How a QPU Works: Qubit Chips, Fridges, Control Pulses and Readout

A quantum processing unit (QPU) is a set of qubits (in superconducting machines, a chip cooled to about 10 mK in a dilution refrigerator) controlled by shaped microwave or laser pulses from classical electronics, and read out by measuring how each qubit shifts a resonator or emits light. Software compiles your circuit into those pulses, and classical computers process every result.

In a superconducting machine of the kind IBM and Google Quantum AI operate, the "processor" you submit a job to is really a stack: a cloud service, a compiler, racks of signal generators and digitisers, a refrigerator with hundreds of coaxial lines running down through five temperature stages, and at the bottom a small chip on which every qubit is a superconducting circuit with a Josephson junction in it. Other machines use single atoms held by lasers, or silicon photonic circuits, but the same layered pattern holds.

This post walks through every layer, with worked numbers checked in Python, dated measured figures from peer-reviewed papers and vendor documentation, and a Bell state traced from a two line circuit down to pulses. It extends our introduction, what quantum computing is: qubits, gates and hardware, and hands off error correction to surface codes, logical qubits and thresholds. For contrast from the GPU side of this series, see AI chip architecture and how a GPU is made: a GPU is a throughput machine for classical arithmetic, while a QPU is an analogue physics experiment wrapped in enough classical control to behave like a programmable device.

Safeguard does not do quantum computing or build or program quantum hardware. The only Safeguard section, near the end, is a short note about the classical software around a QPU and the cryptographic inventory post-quantum migration needs.

Key takeaways

• A QPU system has five layers: the qubit chip, its cryogenic or vacuum environment, the control electronics that make pulses, the readout chain, and the software stack.
• A superconducting transmon is an LC oscillator made nonlinear by a Josephson junction. With a charging energy of 250 MHz and a ratio EJ/EC of 50, the standard formula gives a qubit frequency of about 4.75 GHz and an anharmonicity of about minus 250 MHz.
• At 5 GHz and 4 K the thermal photon number is about 16; at 20 mK it is about 6 × 10⁻⁶. Commercial dilution refrigerators guarantee below 10 mK, with only tens of microwatts of cooling power at 20 mK.
• Control lines need about 60 dB of cold attenuation spread across the 4 K, cold plate and mixing chamber stages to cut room temperature noise to a few thousandths of a photon (Krinner and colleagues, 2019).
• Single-qubit gates are shaped microwave pulses. DRAG adds a derivative-shaped quadrature component; in our three-level simulation of a 20 ns pi pulse it cut leakage from 6.6 × 10⁻⁵ to 2 × 10⁻⁹ at the leakage-optimal setting.
• Readout is dispersive: the qubit shifts a resonator's frequency by around a megahertz. A 2017 experiment reached 98.25% single-shot fidelity in 48 ns.
• Measured figures as of the cited dates: Google's Willow (spec sheet, 9 Dec 2024) has 105 qubits with mean CZ error of 0.33%; Quantinuum's Helios preprint (Nov 2025) reports two-qubit infidelity of 7.9 × 10⁻⁴ across 98 trapped-ion qubits.
• Today's QPUs do not break RSA. The latest public estimate needs fewer than a million noisy qubits for under a week (Gidney, 2025), thousands of times more than any chip here.

What is inside a QPU system?

The word "QPU" is used two ways. Narrowly, it is the chip. Broadly, and in vendor documentation, it is the whole machine you submit a job to. This post uses the broad meaning, because the chip on its own does nothing: it needs a cold, quiet environment, a source of pulses, a way to listen, and a computer to decide what to do next.

Here is the full signal path of a superconducting system, top to bottom. Other modalities differ in the bottom two boxes.

  Your laptop: Python + Qiskit / Cirq            (circuit, observables, shots)
        │  HTTPS job submission
        ▼
  Cloud service and queue                        (auth, scheduling, calibration data)
        │
        ▼
  Compiler / transpiler                          (layout, routing, native gates, timing)
        │  schedule of native operations
        ▼
  Control system at room temperature             (FPGAs, DACs, ADCs, local oscillators,
        │                                          IQ mixers or direct digital synthesis)
        │  microwave drive, flux bias, readout tones
        ▼
 ┌────────────────────── dilution refrigerator ─────────────────────┐
 │ 50 K stage   ── coax, filters                                     │
 │ 4 K stage    ── 20 dB attenuators in, HEMT amplifier out          │
 │ still ~1 K   ── thermal anchoring                                 │
 │ cold plate   ── 20 dB attenuators in                              │
 │ mixing chamber ~10 mK ── 20 dB attenuators, isolators, paramp     │
 │      └── QUBIT CHIP: transmons, couplers, readout resonators      │
 └───────────────────────────────────────────────────────────────────┘
        │  amplified readout signal comes back up
        ▼
  Digitiser + FPGA discrimination                (IQ point → 0 or 1, in real time)
        │
        ├── fast path: feed-forward and real-time decoding (microseconds)
        ▼
  Results: bitstrings, counts, expectation values, error mitigation

The stage temperatures and attenuation values in the box are those reported for a Bluefors XLD400 refrigerator in a published wiring study (Krinner et al., EPJ Quantum Technology, 2019). The overall arrangement of signal creation at room temperature, attenuation on the way down and amplification on the way up follows the reference review by Krantz et al., Applied Physics Reviews, 2019.

The five layers and what each one is for

The rest of the post follows this table row by row.

The qubit chip: transmons, couplers and resonators

From an LC circuit to a qubit

A capacitor and an inductor form a harmonic oscillator with evenly spaced energy levels. That is useless as a qubit, because every transition has the same frequency: a pulse meant to move it from level 0 to level 1 also moves it from 1 to 2, and so on.

A Josephson junction fixes that. It is a thin insulating barrier between two superconductors that Cooper pairs tunnel through, and it acts as a nonlinear inductor. The level spacing becomes uneven, so you can address the bottom two levels alone and call them |0⟩ and |1⟩.

The transmon, introduced by Koch and colleagues in Physical Review A in October 2007, is a Josephson junction shunted by a large capacitor. The large capacitance makes the qubit insensitive to stray electric charge, which was the dominant noise source of earlier charge qubits. The cost is a smaller anharmonicity. The design is governed by two energies:

• EC, the charging energy, set by the total capacitance (EC = e²/2C).
• EJ, the Josephson energy, set by the junction's critical current.

The Krantz review gives the approximate qubit frequency as ħω01 ≈ √(8 EJ EC) minus EC, notes that transmons operate at EJ/EC of 50 or more to suppress charge sensitivity, and gives the anharmonicity α = ω12 minus ω01 as approximately minus EC, typically around 200 to 300 MHz in magnitude.

Worked example 1: designing a transmon frequency

Pick a charging energy of EC/h = 250 MHz and a ratio EJ/EC = 50, so EJ/h = 12.5 GHz.

• √(8 × 12.5 GHz × 0.25 GHz) = √25 GHz² = 5.00 GHz
• Subtract EC: 5.00 minus 0.25 = 4.75 GHz for the 0 to 1 transition
• Anharmonicity: about minus 250 MHz, so the 1 to 2 transition sits near 4.50 GHz

That 250 MHz gap is the entire reason the device can be a qubit. A control pulse has to be spectrally narrow enough to drive 4.75 GHz without touching 4.50 GHz, which pushes gate times towards tens of nanoseconds and motivates the DRAG pulse shaping covered below. Check it yourself: the Python in the worked numbers script near the end prints transmon f01 GHz 4.75.

Fixed-frequency versus tunable qubits

Replace the junction with two junctions in a loop (a SQUID) and an on-chip flux line can tune the qubit frequency. Tunability helps dodge defects and enables flux-driven gates, but adds flux noise. Fixed-frequency transmons avoid flux noise but need all-microwave two-qubit gates. Both are in production use.

Couplers

Two qubits must interact during an entangling gate and not otherwise. Current chips use tunable couplers: an extra circuit element between each pair whose flux-adjusted frequency switches the effective coupling on for a gate and close to zero otherwise. IBM's documentation describes Nighthawk as reusing "couplers, signal delivery, and coherence" technology from Heron, which tells you couplers are a named, first-class part of the processor design (IBM Quantum, processor types).

Readout resonators and Purcell filters

Each transmon is coupled to its own superconducting resonator, tuned a gigahertz or two away from the qubit. Several resonators share one feedline at different frequencies, so one pair of cables reads many qubits (frequency multiplexing). A Purcell filter stops qubit energy leaking out through the readout path.

Layout and connectivity

Sources: IBM Quantum processor types (read 25 Oct 2026) and the Willow spec sheet. IBM's page states the qubit counts and revision dates listed; it does not, on that page, publish per-qubit error figures, so none are quoted here for Heron or Nighthawk.

Heavy-hex connectivity (two or three neighbours) reduces frequency collisions for fixed-frequency qubits. A square grid (four neighbours) suits the surface code and needs fewer SWAPs. The choice follows the gate scheme and error correction plan.

Why the chip lives inside a dilution refrigerator

Worked example 2: thermal population at different temperatures

A qubit at frequency f is only reliably in |0⟩ if the thermal energy kBT is much smaller than the photon energy hf. The ratio hf/kBT and the Bose-Einstein occupation n = 1/(e^(hf/kBT) minus 1) tell you how many thermal photons are present. For f = 5 GHz, hf/kB is 0.240 K, or 240 mK.

At 4 K a 5 GHz qubit is a coin toss. Only below about 50 mK does the ground state dominate overwhelmingly, which is why Krantz and colleagues describe typical operation at "dilution refrigerator temperatures T ≈ 20 mK". In practice measured residual excited populations are higher than this table suggests, because the qubit is coupled to lines and materials that are hotter than the mixing chamber; the next sections are about keeping that coupling small.

How a dilution refrigerator gets to 10 mK

A modern "dry" dilution refrigerator uses no liquid helium bath. Pulse tube cryocoolers cool the 50 K and 4 K stages, and a closed loop of helium-3 and helium-4 mixture does the rest. Bluefors, one maker of these refrigerators, describes its systems as providing continuous cooling at ultra-low temperatures through the dilution of a helium-3 and helium-4 mixture in a closed loop (Bluefors, dilution refrigerator measurement systems).

In outline:

1. Helium-3 gas is compressed at room temperature, pre-cooled by the pulse tubes and condensed.
2. It passes through flow impedances and heat exchangers, cooling as it goes.
3. In the mixing chamber, at these temperatures the mixture separates into a helium-3-rich phase floating on a helium-4-rich phase. Helium-3 atoms crossing from the rich phase into the dilute phase absorb heat, much as evaporation cools a liquid. This is the cooling step.
4. The dilute phase connects to the still, held near 1 K, where helium-3 evaporates preferentially (it has a much higher vapour pressure than helium-4) and is pumped back to room temperature to start again.

Cooling power at the bottom is tiny. Bluefors' published table guarantees a base temperature below 10 mK on most models, with more than 10 to more than 30 µW at 20 mK and more than 250 to more than 1,000 µW at 100 mK, depending on model. Every cable, attenuator and amplifier at the bottom must fit inside that budget.

The temperature stages, measured

Krinner and colleagues published the stage temperatures and cooling powers of their Bluefors XLD400 after installation, noting the values "are typical for state of the art pulse tube cooler based dilution refrigerators":

Source: Table 1 of Krinner et al., 2019. Notice the ratio: the 4K plate can absorb watts, the mixing chamber only microwatts. Anything that dissipates power, including the attenuators themselves, belongs as high up the fridge as possible.

Worked example 3: why drive lines need about 60 dB of cold attenuation

A coaxial cable from room temperature carries thermal noise as well as your signal. At 6 GHz (between a 5 GHz qubit and a 7 GHz resonator, the frequency Krinner and colleagues use), a 300 K line carries about 1,041 thermal photons per mode. An attenuator thermalised at temperature T behaves like a beamsplitter: with attenuation A, it passes a fraction 1/A of what arrives and adds (A minus 1)/A of its own blackbody occupation. Krinner's Equation 3 writes this as nᵢ = nᵢ₋₁/Aᵢ + (Aᵢ minus 1)/Aᵢ × nBE(Tᵢ).

Applying it with 20 dB (A = 100) at each of three stages, using the measured stage temperatures above:

The lower bound Krinner and colleagues give, ignoring each attenuator's own emission, is nBE(300 K)/10⁻³, which is 60.2 dB. Our cascade lands at about 2.3 × 10⁻³ photons, consistent with their statement that 60 dB brings the line to "a thermal photon occupation number of a few 10⁻³". Every one of those decibels is signal power turned into heat, which is why the attenuation is split across stages: 99% of the power reaching a 20 dB attenuator is dissipated in it.

Wiring is a scaling problem

Each qubit needs a drive line, often a flux line, and a share of readout lines. Across hundreds of qubits, the passive heat leak down each cable and the active heat from attenuators consume the cooling budget. IBM's Heron description mentions "high-density flex cabling", and the Krinner study measured coax heat loads precisely because wiring is a scaling limit.

Control electronics and microwave pulses

How a gate becomes a waveform

A single-qubit gate on a transmon is a Rabi rotation: drive the qubit at its 0 to 1 frequency and the state rotates around an axis on the Bloch sphere. The rotation angle is set by the pulse's area (amplitude times duration, for a constant envelope), and the axis is set by the pulse's phase. So a gate is a microwave burst at a few gigahertz with a carefully shaped envelope and a chosen phase.

Electronics build that burst with IQ modulation. A digital-to-analogue converter produces two envelope signals, I (in phase) and Q (quadrature), at an intermediate frequency; an IQ mixer multiplies them by a local oscillator so the result lands on the qubit frequency. Newer systems often synthesise the gigahertz signal directly with fast converters, but the I and Q description is unchanged.

   I(t) ──┐                                 drive at ωLO + ωIF
          ├── IQ mixer ── filter ── 60 dB of cold attenuation ── qubit
   Q(t) ──┘      ▲
                 │
          local oscillator ωLO

   Gate          Envelope on I              Envelope on Q        Phase
   X (π)         Gaussian, area π           DRAG derivative      0°
   Y (π)         Gaussian, area π (on Q)    DRAG derivative      90°
   √X (π/2)      Gaussian, area π/2         DRAG derivative      0°
   RZ(θ)         nothing played             nothing played       software phase shift

Virtual Z gates

Rotations around Z need no pulse. Because each later X or Y rotation's axis is set by its pulse phase, RZ(θ) is just a θ shift of that qubit's phase reference. Krantz and colleagues call these "virtual Z gates": effectively perfect and zero duration. Compilers rely on this heavily.

DRAG: derivative removal by adiabatic gate

The transmon's small anharmonicity creates a problem. A short pulse has a wide spectrum, and part of that spectrum reaches the 1 to 2 transition only 200 to 300 MHz away. Two errors follow, as Krantz and colleagues describe: leakage out of the computational subspace into |2⟩, and phase errors, because the drive pushes the 1 and 2 levels apart and so shifts the 0 to 1 frequency during the pulse.

Motzoi, Gambetta, Rebentrost and Wilhelm (Physical Review Letters, September 2009) proposed adding a second control "proportional to the time-derivative of the first". In Krantz's form, the envelope s(t) on I is paired with λ ṡ(t)/α on Q; λ = 0.5 is theoretically optimal for the phase error and λ = 1 for leakage, and in practice λ is calibrated because cables distort the pulse.

Worked example 4: simulating a DRAG pulse on a three-level transmon

We simulated a 20 ns Gaussian pi pulse (σ = 5 ns) on a three-level transmon with α/2π = minus 200 MHz, the anharmonicity in Krantz's figure, in the frame rotating at the 0 to 1 frequency. It is an idealised model: no decoherence, no line distortion, no other qubits.

| DRAG scale λ | P(|0⟩) after pulse | P(|1⟩), the target | P(|2⟩), leakage | |---|---|---|---| | 0 (plain Gaussian) | 1.01 × 10⁻² | 0.98986 | 6.6 × 10⁻⁵ | | 0.5 | 4.5 × 10⁻⁵ | 0.99994 | 1.7 × 10⁻⁵ | | 1.0 | 1.05 × 10⁻² | 0.98950 | 2.1 × 10⁻⁹ | | minus 1.0 (wrong sign) | 9.0 × 10⁻² | 0.90985 | 2.4 × 10⁻⁴ |

Three lessons fall out, and all three match the review's description:

• The plain Gaussian already leaks only 6.6 × 10⁻⁵ at this speed, but it misses the target by about 1%: that is the drive-induced frequency shift, a phase error, not leakage.
• λ = 0.5 fixes the phase error and gets the transition right to six parts in 100,000 in this model.
• λ = 1 nearly eliminates leakage but leaves the phase error, which in a real calibration is removed with a small frequency detuning of the pulse or a virtual Z correction. Krantz and colleagues describe exactly that combination.

The peak Rabi frequency is about 47 MHz. The code is near the end; it ran on this Mac and is a model, not a measurement of any device.

Two-qubit gates

There are two broad families, as the Krantz review lays out.

• Flux-activated gates on tunable qubits or couplers. Bringing |11⟩ near resonance with |02⟩ for exactly the right time puts a phase of π on |11⟩ alone: a controlled-Z (CZ) gate. Google's Willow spec sheet reports its error correction chip's two-qubit operation as CZ, with a mean simultaneous error of 0.33% ± 0.18%, and its random circuit sampling chip as an "iswap-like" gate with mean error 0.14% ± 0.052%.
• All-microwave gates on fixed-frequency qubits. The cross-resonance gate drives one qubit at its neighbour's frequency, producing a conditional rotation. IBM's older processors exposed it as the ECR (echoed cross-resonance) gate; IBM's transpilation guide still shows example output containing "RZ, X, SX, and ECR gates", while its fractional gates guide describes Heron circuits in terms of CZ gates and adds native RZZ(θ) for 0 to π/2 and RX(θ) for any angle when a backend is loaded with use_fractional_gates=True (IBM Quantum, fractional gates).

Calibration never stops

Qubit frequencies drift as microscopic material defects (two-level systems) move, and amplitudes and readout thresholds drift too. A production QPU reruns calibrations (Rabi, Ramsey, DRAG and readout scans) on a schedule and publishes the results, which the compiler uses to pick physical qubits. That is why the same circuit can land on different qubits on different days.

Readout: turning a qubit state into a bit

Dispersive measurement

You cannot just "look" at a transmon. Instead, each qubit is detuned from its readout resonator by a gigahertz or so. In that dispersive regime the qubit and resonator do not exchange energy, but the resonator's frequency depends on the qubit's state. The Blais et al. review of circuit QED (Reviews of Modern Physics, May 2021) covers the theory, and Krantz and colleagues give the practical version: in a simple two-level model the shift is χ = g²/Δ, and including the transmon's higher levels it becomes, in magnitude, |χ| = g²|α| / |Δ(Δ + α)|, where g is the qubit to resonator coupling and Δ is the qubit to resonator detuning. The sign of χ depends on the convention and the regime; what matters for readout is its size.

Worked example 5: how far apart are the two resonator frequencies?

Take a qubit at 5.0 GHz, a resonator at 7.0 GHz (so Δ/2π = minus 2.0 GHz), coupling g/2π = 100 MHz and anharmonicity α/2π = minus 300 MHz:

• g² = 0.01 GHz²
• |Δ(Δ + α)| = 2.0 × 2.3 = 4.6 GHz²
• |χ|/2π = 0.01 × 0.3 / 4.6 = 0.65 MHz
• The resonator frequency differs by 2χ, about 1.3 MHz, between |0⟩ and |1⟩

A 1.3 MHz shift on a 7 GHz resonator is a change of about two parts in 10,000. To see it you send a short tone at a frequency between the two possibilities, and look at the phase and amplitude of what comes back. Plotted in the I and Q plane, repeated measurements form two clouds, one for each state. The discriminator draws a line between them.

The amplifier chain

The readout tone is weak, a few photons, because a strong tone causes unwanted transitions. Krantz and colleagues note that a HEMT amplifier at 4 K (noise temperature about 2 K) gives a system noise temperature of 7 to 10 K, "around 10-20 added photons of noise per signal photon around 5 GHz", which is "generally too much noise to perform single-shot readout". The fix is a quantum-limited parametric amplifier at the mixing chamber, such as a Josephson travelling wave parametric amplifier (TWPA) made of a few thousand junction unit cells, that adds close to the minimum noise quantum mechanics allows. Isolators between the chip and the amplifier stop amplifier noise flowing backwards into the qubits.

  qubit ── resonator ── Purcell filter ── feedline ── isolator ── TWPA (10 mK)
                                                                    │
                                    HEMT amplifier (4 K) ◄──────────┘
                                         │
                       room temperature amplifiers, downconversion, ADC
                                         │
                         FPGA: integrate trace → IQ point → 0 or 1

Worked example 6: speed versus fidelity in readout

Walter et al. (Physical Review Applied, May 2017) combined a strong dispersive shift, an optimised resonator linewidth, a Purcell filter and a phase-sensitive parametric amplifier. They report "98.25% readout fidelity in only 48 ns" and "99.2% in 88 ns", "limited predominantly by the qubit lifetime of 7.6 us". The arithmetic shows why lifetime is the limit: with T1 = 7.6 µs, the probability of decay during the measurement is 1 minus e^(minus t/T1), which is 0.63% for 48 ns and 1.15% for 88 ns. A qubit in |1⟩ that decays halfway through is read as 0, so faster readout or longer T1 directly improves assignment fidelity.

Readout is still the noisiest operation on most superconducting chips. Willow's spec sheet reports a mean simultaneous measurement error of 0.77% ± 0.21% on its error correction chip, more than twice its 0.33% two-qubit gate error.

Reset

Waiting several T1 for a qubit to relax wastes time, so systems use active reset: measure and flip, or pump the excitation out through the resonator. Willow lists "Multi-level reset (|1⟩ state and above)" and "Leakage removal (|2⟩ state only)". IBM's description of Nighthawk r2 calls out "a high speed reset on each qubit which significantly increases the maximum number of circuits per second".

Classical feedback and real-time decoding

Error correction and many algorithms need decisions mid-circuit: measure, then choose the next operation from the result, within a fraction of the coherence time. That logic runs in FPGAs in the control system, not on the user's computer.

Error correction is the extreme case. The Google Quantum AI surface code paper (Nature, published online 9 December 2024) runs a cycle every 1.1 µs, which the Willow spec sheet expresses as 909,000 error correction cycles per second, and reports a real-time decoder with "average decoder latency of 63 μs at distance-5 up to a million cycles". Decoding is classical computation, and keeping it fast enough is a large part of the system design.

Worked example 7: the idle-time budget

Willow's error correction chip lists a mean T1 of 68 µs. If a qubit did nothing but wait for one 1.1 µs cycle, the chance it would relax from |1⟩ is 1 minus e^(minus 1.1/68), about 1.6%, and there are only about 62 such cycles in one T1. That is why the cycle is packed so tightly and why error correction must catch errors continuously rather than at the end. (The 1.6% illustrates the time scale; it is not a measured error rate.)

One shot, start to finish

 time ─────────────────────────────────────────────────────────────────────►
 reset    │ gates (tens of ns each, RZ free) │ readout (~tens to hundreds of ns) │ classify │ next shot
 ▓▓▓▓▓▓▓▓ │ ░░ ░░ ████ ░░ ░░ ████ ░░          │ ≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈≈                    │ FPGA     │ ▓▓▓▓
          │ ░ = single-qubit DRAG pulse      │ ≈ = resonator tone, integrate IQ   │ 0 or 1   │
          │ █ = two-qubit flux or CR pulse   │                                    │          │

Thousands of these shots run per second. Willow's random circuit sampling chip lists 63,000 circuit repetitions per second. The result returned to you is a histogram of bitstrings, from which expectation values are estimated.

Other qubit modalities

Superconducting circuits are one of several approaches with published, peer-reviewed results. The same five layers apply to each: a physical qubit, an environment that isolates it, a way to apply gates, a way to measure, and a classical stack. What changes is the physics in each layer.

Trapped ions

Each qubit is a single ion (barium-137 in Quantinuum's Helios, for example) held in vacuum by electric fields from trap electrodes. Gates use lasers or microwaves, with the ions' shared motion as the bus for two-qubit gates. Measurement uses state-dependent fluorescence: one state glows under a laser, the other stays dark.

Ions are identical by nature and coherence times are long; the cost is speed, since gates and ion transport are far slower than superconducting gates. The quantum charge-coupled device (QCCD) architecture moves ions between zones for storage, gates and measurement.

• Quantinuum's H2 race-track processor (Moses et al., Physical Review X, December 2023) was "initially operated with 32 qubits" and reported average single-qubit gate infidelity of 2.5 × 10⁻⁵, two-qubit infidelity of 1.84 × 10⁻³ and state preparation and measurement error of 1.6 × 10⁻³.
• Quantinuum's Helios (arXiv preprint, 7 November 2025; a version was published in Nature in June 2026) uses 98 barium-137 ions with "all-to-all connectivity enabled by a rotatable ion storage ring", and reports averages of 2.5 × 10⁻⁵ for single-qubit gates, 7.9 × 10⁻⁴ for two-qubit gates and 4.8 × 10⁻⁴ for state preparation and measurement. That two-qubit figure is a fidelity of 99.921%.
• The same group demonstrated logical qubits with error rates below physical ones in 2024 (arXiv 2404.02280).

Neutral atoms

Each qubit is a single neutral atom, such as rubidium, held in a focused laser beam (an optical tweezer) in a vacuum cell; arrays of hundreds can be rearranged by moving the beams. Two-qubit gates use Rydberg states, very high energy levels at which neighbouring atoms interact strongly. Measurement is by fluorescence imaging.

• Evered et al., Nature, October 2023: two-qubit entangling gates "with 99.5% fidelity on up to 60 atoms in parallel".
• Bluvstein et al., Nature, December 2023: a "programmable quantum processor based on encoded logical qubits operating with up to 280 physical qubits", including up to 48 logical qubits in sampling circuits and surface code distance scaling from 3 to 7.

Atoms can be moved, so connectivity is reconfigurable. The trade-offs are slower cycle times than superconducting chips and atom loss, which has to be detected and replaced.

Photonic qubits

Here the qubit is a photon, for example in "dual-rail" encoding where one photon occupies one of two waveguides. Photons barely decohere, and much of the hardware is silicon photonics from commercial fabs. The hard parts are making single photons on demand, avoiding loss, and making photons interact, done in measurement-based schemes with "fusion" measurements. Many photonic designs use superconducting single-photon detectors, so cryogenics does not disappear entirely.

• PsiQuantum's team in Nature, February 2025 benchmarked manufactured modules: dual-rail qubits with 99.98% ± 0.01% state preparation and measurement fidelity, two-qubit fusion at 99.22% ± 0.12% and a chip-to-chip interconnect at 99.72% ± 0.04%, figures the authors state are "not accounting for loss".

That caveat matters: for photonics, loss is the dominant error, and fidelity figures without loss are not directly comparable with gate fidelities on matter qubits.

Spin qubits in silicon

A spin qubit stores information in the spin of a single electron (or hole) confined in a quantum dot, a tiny potential well formed by gate electrodes on a silicon chip. These devices look much like transistors, which is the attraction: in principle they can use semiconductor manufacturing. They usually run in a dilution refrigerator, and are controlled by microwave magnetic or electric fields.

• Xue et al., Nature, January 2022: "single- and two-qubit gate fidelities all above 99.5%, extracted from gate set tomography", in a two-qubit silicon device.

Spin qubit devices so far have far fewer qubits than the other modalities, and uniformity across many dots is an open engineering problem.

Modalities compared

These numbers are not a ranking. They come from different experiments, benchmarking methods and system sizes, and newer results may exist. Use them for orders of magnitude, not to pick a winner.

The software stack: from circuit to pulses

Most users see only an SDK such as Qiskit or Cirq, a circuit and a result. The layers in between explain most surprises on real hardware.

The layers

OpenQASM 3, described by Cross and colleagues in 2021 as "a broader and deeper quantum assembly language", is the common text format at the circuit layer. It adds classical control flow and timing to the earlier OpenQASM 2, which is what lets a program express mid-circuit measurement and feed-forward.

What the transpiler does

Qiskit's documentation describes six default transpiler stages (Qiskit, transpiler stages):

1. init: decompose gates that act on more than two qubits into one- and two-qubit gates, and run any user initial optimisations.
2. layout: map each virtual qubit to a physical qubit. The guide calls this choice "extremely important for minimizing the number of SWAP operations needed" and for using the best-calibrated qubits.
3. routing: insert SWAP gates where the circuit needs two qubits to interact that are not neighbours on the chip.
4. translation: rewrite every gate into the backend's basis set, for example RZ, SX, X and CZ.
5. optimization: cancel and merge gates, and resynthesise blocks into shorter sequences.
6. scheduling: assign start times and insert delays, so that idle periods are explicit and can be filled with error suppression sequences.

The output is what IBM calls an ISA circuit: "instructions that are supported by the backend's Target", complying with the "connectivity of the hardware" (Qiskit, transpile).

Where did pulse-level control go?

Users of IBM hardware once wrote pulse schedules with qiskit.pulse. IBM's migration guide states that pulse-level control on all IBM Quantum processors was deprecated and would be removed in early 2025, and that qiskit.pulse was deprecated in Qiskit SDK 1.3.0 and removed in 2.0.0 (Qiskit, migrate from Qiskit Pulse to fractional gates). The most common use of pulses, building custom single- and two-qubit rotations, is now covered by fractional RX and RZZ gates on Heron, and pulse-level modelling moved to the separate Qiskit Dynamics package.

The pulses still exist; the vendor's control software compiles them from calibrated gate definitions. Some other platforms still expose pulse-level programming.

Worked example 8: a Bell state from circuit to pulses

A Bell state is the simplest entangled state: (|00⟩ + |11⟩)/√2. Measure both qubits and you get 00 or 11 with equal probability, never 01 or 10. Here is how it travels through the stack.

Step 1: the circuit

The code below ran on this Mac with Qiskit 2.2.3 on Python 3.9, using Qiskit's built-in statevector simulator. It did not run on quantum hardware. Qiskit printed a deprecation warning for Python 3.9 (support is scheduled to end in Qiskit 2.3.0), which we suppressed with -W ignore; use a newer Python for anything real.

python3 -m venv qenv
./qenv/bin/pip install qiskit
./qenv/bin/python -W ignore bell.py

# bell.py: build a Bell state, translate it to a Heron-style native gate set,
# and sample it on Qiskit's local statevector simulator (no hardware).
from qiskit import QuantumCircuit, transpile
from qiskit.transpiler import CouplingMap
from qiskit.quantum_info import Statevector
from qiskit.primitives import StatevectorSampler

qc = QuantumCircuit(2)
qc.h(0)
qc.cx(0, 1)
print(Statevector(qc))          # ideal state before measurement
qc.measure_all()

# Translate to a native set of CZ plus RZ, SX and X on two connected qubits
native = transpile(
    qc,
    basis_gates=["cz", "rz", "sx", "x"],
    coupling_map=CouplingMap([[0, 1], [1, 0]]),
    optimization_level=1,
    seed_transpiler=7,
)
print(native.draw(output="text"))
print(dict(native.count_ops()))

result = StatevectorSampler(seed=1234).run([native], shots=4000).result()
print(result[0].data.meas.get_counts())

Step 2: the ideal state

Statevector([0.70710678+0.j, 0.        +0.j, 0.        +0.j,
             0.70710678+0.j],
            dims=(2, 2))

The amplitudes of |00⟩ and |11⟩ are both 1/√2 ≈ 0.7071, and the other two are zero, as expected.

Step 3: translation to native gates

Neither H nor CNOT is native on a CZ machine, so the transpiler rewrites them:

global phase: 3π/4
         ┌─────────┐┌────┐┌─────────┐                                ░ ┌─┐
q_0 -> 0 ┤ Rz(π/2) ├┤ √X ├┤ Rz(π/2) ├─■──────────────────────────────░─┤M├───
         ├─────────┤├────┤├─────────┤ │ ┌─────────┐┌────┐┌─────────┐ ░ └╥┘┌─┐
q_1 -> 1 ┤ Rz(π/2) ├┤ √X ├┤ Rz(π/2) ├─■─┤ Rz(π/2) ├┤ √X ├┤ Rz(π/2) ├─░──╫─┤M├
         └─────────┘└────┘└─────────┘   └─────────┘└────┘└─────────┘ ░  ║ └╥┘
 meas: 2/═══════════════════════════════════════════════════════════════╩══╩═
                                                                        0  1
{'rz': 6, 'sx': 3, 'measure': 2, 'cz': 1, 'barrier': 1}

The Hadamard on qubit 0 became RZ(π/2), √X, RZ(π/2). The CNOT became a CZ between Hadamard-equivalent sequences on the target, qubit 1. The transpiler kept all six RZ gates because they are free.

Step 4: from native gates to pulses

Now map each native operation to what the control system plays. The durations of production gates on any specific IBM or Google processor are reported by the backend at run time and change with calibration, so we show the schedule by kind of pulse, not by nanoseconds.

So the whole Bell state is three physical single-qubit pulses, one two-qubit pulse and two multiplexed readout tones. Everything else is bookkeeping in the phase registers of the control system.

 q0 drive  │ ░√X░ │          │                 │
 q1 drive  │ ░√X░ │          │ ░√X░            │
 coupler   │      │ ████CZ██ │                 │
 readout   │      │          │      │ ≈≈≈≈≈≈≈≈≈≈≈≈≈ q0, q1 multiplexed
 phase     RZ    RZ          RZ    RZ  (zero-duration frame changes)

Step 5: the result

{'11': 2034, '00': 1966}

The ideal simulator returns only 00 and 11, in roughly equal numbers, which is the Bell state signature. On hardware you would also see some 01 and 10.

Step 6: a rough error budget on real hardware

How many? A back-of-envelope estimate multiplies one minus each operation's error. Using the mean errors on Willow's error correction chip (spec sheet, 9 Dec 2024): single-qubit 0.035%, CZ 0.33%, measurement 0.77%.

• Three single-qubit pulses: (1 minus 0.00035)³ ≈ 0.99895
• One CZ: 0.9967
• Two measurements: (1 minus 0.0077)² ≈ 0.98466
• Product: about 0.980

So roughly 2% of shots would show an error, mostly from readout. This is an order-of-magnitude guide only: randomized benchmarking reports an average error per gate, errors are not independent, and your qubits may differ from the chip mean. We have not run this circuit on Willow or any other device.

Error rates and error correction

Physical error rates of 0.1% to 1% sound small, but useful algorithms need billions of operations. The known route is quantum error correction: encode one logical qubit in many physical ones and decode error syndromes in real time.

The milestone that matters is operating "below threshold", where adding more physical qubits makes the logical qubit better rather than worse. The Google Quantum AI paper of December 2024 reports a distance-7 surface code using 101 qubits with "0.143% ± 0.003% error per cycle", a suppression factor Λ = 2.14 ± 0.02 each time the code distance rises by two, and a logical memory "beyond break-even", lasting 2.4 ± 0.3 times longer than its best physical qubit. Neutral atom and trapped-ion groups have published their own logical qubit results, cited above.

Stabilisers, decoders and thresholds are covered in our quantum error correction explainer. The hardware view adds one point: every layer here feeds the logical error rate, from wiring heat and readout error to reset speed and decoder latency.

What QPUs can and cannot do today

It is worth being plain about this, because headlines are not.

Demonstrated: sampling tasks the authors argue are beyond classical simulation (Willow's spec sheet cites "5 minutes vs. 10²⁵ years" for random circuit sampling, against a classical estimate, not a useful application); below-threshold error correction on small codes; and logical qubits that beat physical ones in specific experiments.

Not demonstrated: breaking any cryptography in use today. Today's QPUs do not break RSA. Shor's algorithm (SIAM Journal on Computing, October 1997) would factor large numbers efficiently on a large, error-corrected machine. The most recent public resource estimate, by Craig Gidney (arXiv, May 2025), is that "a 2048 bit RSA integer could be factored in less than a week by a quantum computer with less than a million noisy qubits", assuming a 0.1% gate error rate, a 1 µs surface code cycle and a 10 µs control reaction time.

A million qubits is about 9,500 times Willow's 105 and about 6,400 times Heron's 156. The best error rates are near the 0.1% assumption, but nobody has built a machine at that scale; doing so means solving the wiring, cooling, control and decoding problems above thousands of times over.

That is still a reason to act. Data encrypted today can be recorded and decrypted later, and replacing cryptography across a software estate takes years. NIST published its first post-quantum standards, including FIPS 203 (ML-KEM), on 13 August 2024, and its draft transition guidance, NIST IR 8547 (initial public draft, 12 November 2024), proposes deprecating and then disallowing quantum-vulnerable public key algorithms. Our post on quantum computers and cryptography explains the migration in detail.

Check the numbers yourself

Every computed figure in this post came from the two scripts below, run on this Mac. The first uses only the Python standard library; the second needs NumPy and SciPy, which the pip install qiskit step above already pulled in. Both are simple physics models, not hardware measurements.

# nums.py: worked numbers for thermal population, wiring, transmon design,
# dispersive shift, idle decay and the Bell error budget.
import math
h = 6.62607015e-34      # Planck constant, exact SI value
kB = 1.380649e-23       # Boltzmann constant, exact SI value

def n_be(f, T):
    return 1 / (math.exp(h * f / (kB * T)) - 1)

for T in [300, 4, 0.1, 0.02, 0.01]:
    x = h * 5e9 / (kB * T)
    p = math.exp(-x) / (1 + math.exp(-x))
    print(f"T={T} K hf/kT={x:.4g} n={n_be(5e9, T):.4g} P1={p:.3g}")

# Krinner et al. Eq. 3, 20 dB at 4K (2.85 K), CP (82 mK), MXC (6 mK), 6 GHz
n = n_be(6e9, 300)
for A_dB, T in [(20, 2.85), (20, 0.082), (20, 0.006)]:
    A = 10 ** (A_dB / 10)
    n = n / A + (A - 1) / A * n_be(6e9, T)
    print(f"after {A_dB} dB at {T} K: n={n:.4g}")
print("lower bound dB:", 10 * math.log10(n_be(6e9, 300) / 1e-3))

EC = 0.25; EJ = 50 * EC                       # GHz
print("transmon f01 GHz", math.sqrt(8 * EJ * EC) - EC)

g, D, a = 0.1, 5.0 - 7.0, -0.3                # GHz
chi = g**2 * abs(a) / abs(D * (D + a))
print("|chi| MHz", chi * 1e3, "2chi MHz", 2 * chi * 1e3)

print("idle decay per 1.1 us at T1=68 us", 1 - math.exp(-1.1 / 68))
for t in [48e-9, 88e-9]:
    print("readout decay", t, 1 - math.exp(-t / 7.6e-6))
print("Bell budget", (1 - 0.00035) ** 3 * (1 - 0.0033) * (1 - 0.0077) ** 2)
print("1e6 / 105 =", 1e6 / 105, " 1e6 / 156 =", 1e6 / 156)

# drag.py: three-level transmon driven by a 20 ns Gaussian pi pulse,
# with and without DRAG. Idealised model: no decoherence, no distortion.
import numpy as np
from scipy.linalg import expm

alpha = 2 * np.pi * (-200e6)          # anharmonicity in rad/s
T, sigma, N = 20e-9, 5e-9, 4000
t = np.linspace(0, T, N + 1); dt = t[1] - t[0]; tm = t[:-1] + dt / 2

def gauss(x):
    g = np.exp(-(x - T / 2) ** 2 / (2 * sigma ** 2))
    g0 = np.exp(-(T / 2) ** 2 / (2 * sigma ** 2))
    return (g - g0) / (1 - g0)          # starts and ends at zero

a = np.diag([1, np.sqrt(2)], 1); ad = a.T
H0 = np.diag([0, 0, alpha])            # frame rotating at the 0-1 frequency
s = gauss(tm); amp = np.pi / (np.sum(s) * dt)

def run(lam):
    sx = amp * s
    sy = -lam * amp * np.gradient(gauss(tm), tm) / alpha
    U = np.eye(3, dtype=complex)
    for k in range(N):
        H = H0 + 0.5 * sx[k] * (a + ad) + 0.5 * sy[k] * (1j * ad - 1j * a)
        U = expm(-1j * H * dt) @ U
    return np.abs(U[:, 0]) ** 2         # populations after starting in |0>

print("peak Rabi MHz", amp / (2 * np.pi) / 1e6)
for lam in [0, 0.5, 1.0, -1.0]:
    p = run(lam)
    print(f"lambda={lam:+.1f} P0={p[0]:.2e} P1={p[1]:.6f} P2={p[2]:.2e}")

The DRAG script printed P2 of 6.64e-05 at λ = 0, 1.70e-05 at 0.5, 2.12e-09 at 1.0 and 2.40e-04 at minus 1.0, and a peak Rabi frequency of about 46.7 MHz, which are the values in the table earlier.

Common mistakes

• Treating qubit count as performance. A chip with more qubits but higher error rates may run fewer useful operations. Look at gate errors, readout error, connectivity and coherence together, with their dates.
• Comparing fidelities across modalities directly. Benchmarking methods differ, and photonic figures "not accounting for loss" are not comparable with matter-qubit gate fidelities.
• Assuming all gates cost time. RZ is virtual on superconducting hardware. Counting RZ gates as depth overestimates runtime and misdirects optimisation.
• Ignoring readout error. On many chips measurement is the noisiest operation. Readout error mitigation and careful qubit selection often help more than gate tweaks.
• Forgetting layout. On a grid or heavy-hex chip, each SWAP costs three two-qubit gates. Let the transpiler pick qubits from current calibration data.
• Relying on removed APIs. Code written for qiskit.pulse will not run on Qiskit 2.x. Pin your SDK version and read the migration guides before upgrading.
• Overstating the threat or dismissing it. Today's machines do not break RSA, and yet migration to post-quantum cryptography should already be planned, because it takes years.

FAQ

What is a QPU?

A QPU, or quantum processing unit, is the part of a quantum computer that holds and manipulates qubits. In vendor usage it often means the whole system: the qubit chip, its cryogenic or vacuum environment, the control electronics, the readout chain and the software that compiles and runs circuits.

Why do quantum computers need to be so cold?

Superconducting qubits work at about 5 GHz, and at that frequency thermal energy swamps the qubit unless the temperature is far below 240 mK. At 20 mK the thermal photon number is about 6 × 10⁻⁶; at 4 K it is about 16. Cooling also keeps the metal superconducting and suppresses losses.

What is a transmon qubit?

A transmon is a superconducting circuit: a Josephson junction shunted by a large capacitor, introduced in 2007. The junction makes the energy levels unevenly spaced, so the lowest two levels can be used as a qubit. The large capacitor makes it insensitive to charge noise.

How are quantum gates applied to superconducting qubits?

Single-qubit gates are shaped microwave pulses at the qubit frequency, usually with DRAG shaping to avoid leakage. Z rotations are virtual phase changes. Two-qubit gates use flux pulses on tunable couplers or qubits (for example CZ) or microwave cross-resonance drives on fixed-frequency qubits.

How is a qubit measured?

Each superconducting qubit is coupled to a microwave resonator whose frequency depends on the qubit state. A short tone probes the resonator, a parametric amplifier and a HEMT amplifier boost the reflected signal, and electronics classify the result as 0 or 1. Ions and atoms are measured by detecting fluorescence.

What is the difference between superconducting, trapped-ion and neutral atom quantum computers?

Superconducting qubits are fabricated circuits in a dilution refrigerator with fast gates. Trapped-ion qubits are single ions in vacuum, identical and long-lived but slower. Neutral atom qubits are atoms held in laser tweezers, reconfigurable into large arrays. Each has published two-qubit fidelities above 99%, measured in different ways.

Can a quantum computer break RSA today?

No. The most recent public estimate for factoring 2048-bit RSA needs fewer than a million noisy qubits running for under a week. The largest chips described here have about a hundred to a few hundred physical qubits. Post-quantum migration should still be planned now because it takes years.

What software do you use to program a QPU?

Most users write circuits in Python SDKs such as Qiskit or Cirq, or in OpenQASM 3. A transpiler maps the circuit to the device's native gates and connectivity, and the vendor's control software turns those gates into pulses.

The software around QPUs: an honest bridge

Safeguard does not do quantum computing. It does not design, calibrate, simulate or program quantum processors, and it does not speed up any quantum or classical computation. What it does touch is the ordinary classical software that surrounds this field, and the cryptographic inventory that the post-quantum transition needs.

First, the quantum software stack is open source Python and C++: SDKs, simulators, NumPy, SciPy, Jupyter and the web services that submit jobs. Those are dependencies with versions and CVEs like any others, and the qenv above is one more environment to keep current. Safeguard generates and analyses SBOMs in SPDX and CycloneDX formats and matches components against vulnerability databases, so a research group or a platform team can see which projects carry which versions. Second, a post-quantum plan starts with knowing which cryptographic libraries and versions your software ships. An SBOM is an inventory of components rather than of every algorithm call, so it is a starting point for that work, not the whole of it; Safeguard's policy catalogue includes a Crypto Algorithm Audit internal policy among its compliance checks.

The section below is the same for every Safeguard post, because the gap it addresses is the same: dependencies with known fixes that are not yet deployed, and dependencies with no upstream fix at all.

More in this series

Other posts in our GPUs, CPUs, QPUs and lithography series:

• AMD GPU Architecture Explained: GCN, RDNA, CDNA, Infinity Fabric and HIP
• CPU vs GPU vs QPU Explained: How Each Works and Why They Coexist
• CUDA Programming Model Explained: Grids, Blocks, Warps and Memory
• GPU Memory and Interconnects: HBM, GDDR, NVLink, PCIe, CXL
• CUDA vs HIP vs SYCL vs OpenCL vs Metal vs Vulkan vs Triton Compared
• GPU Software Supply Chain: Drivers, CUDA, cuDNN, NCCL and Your SBOM
• How CPUs Work: Pipelines, Out-of-Order, Caches, Branches, SIMD
• How EUV Lithography Machines Work: Tin Plasma, Mirrors and High-NA
• How GPUs Work: Graphics Pipeline, Shader Cores, Ray Tracing and Compute
• Inside an NVIDIA SM: Warp Schedulers, Registers, Tensor Cores
• Intel GPU Architecture: Xe Cores, XMX, Ponte Vecchio and oneAPI SYCL
• NVIDIA GPU Architecture History: From Tesla and Fermi to Blackwell
• NVIDIA vs AMD vs Intel vs Apple GPUs: Architectures Compared
• Optimizing a CUDA Matrix Multiply Step by Step, From Naive to Tensor Cores
• Photolithography Explained: Contact Printing to DUV Immersion and Overlay
• Tile-Based GPUs Explained: Apple, Mali, Adreno, PowerVR and TBDR

Fix it without waiting for upstream

Whatever the vulnerability, most of the risk sits in two gaps. The first is the time between a fix being published and that fix actually running in your production builds. The second, and worse, is the time before any fix exists at all, while a maintainer works out a patch and a release schedule. Waiting through both gaps is a habit, not a requirement. Safeguard gives teams three ways to close them.

1. Autonomous remediation: pull requests, not tickets

When a fixed version exists, Safeguard's Griffin models open a tested, policy gated pull request that moves the affected dependency to the safe version. You can run it on one repository or in bulk across every project that carries the vulnerable version. Remediation covers eight categories, including dependencies, licenses, security posture and findings. Reachability analysis ranks the vulnerable code paths your application actually calls first, so the first pull requests you merge are the ones that matter most. Autonomous remediation ships switched off, with every category set to Manual, so your team decides how much runs on its own and what still needs a human approval.

2. Gold Open Source: the safe version in seconds, free

gold.safeguard.sh is free and needs no login. Search any CVE or package to see affected and fixed versions, CVSS, EPSS, CISA KEV status and a recommended safe version, or use the "Am I affected?" checker. The same data is available through a free read API, README status badges and RSS threat feeds. The safeguard-sh/gold-scan-action GitHub Action can fail a build on a known exploited vulnerability, on any known vulnerability, or never, so a version you have just removed cannot quietly come back in next week's merge.

3. Gold Registry: start from components that are already fixed

registry.safeguard.sh provides hardened, drop in replacements for upstream packages and container images. Every Gold artifact is held continuously to zero exploitable critical or high CVEs, zero malware and a completed license check, with SLSA L3 or higher provenance, a Sigstore signature and a public evidence page you can hand to an auditor. An artifact loses its Gold badge if it regresses. Teams can point their own package directory at the registry so hardened equivalents resolve without changing how developers install anything.

When upstream has no fix yet, or will not ship one, Safeguard first works to get the fix accepted upstream. If the issue is severe or upstream will not move, Safeguard builds a fork, fixes the vulnerability there and publishes a hardened Gold build, so you are not stuck on a maintainer's release schedule. You can also request a hardened, compatibility tested build of a specific package. This fork and patch flow is in early access today, so ask which packages it covers before you plan around it.

One honest limit: when the vulnerable code lives in a vendor appliance, a hosted service or an operating system runtime you do not build yourself, the fix still has to come from that vendor or distribution. The steps above apply to the open source dependencies and container images you build and ship, which is where most teams carry the largest and least tracked share of their exposure.

See how Safeguard would help

None of these demos involve quantum hardware, pulse control or quantum algorithms. They show the classical software side described in the bridge above.

The first demo is a real Safeguard CLI session. It installs the CLI, opens the interactive terminal and asks it to fix a lodash CVE in a repository; it reads the finding and the advisory, asks before any command that changes something, edits package.json to lodash 4.17.21, runs npm install and npm test with approval, prints a summary and pushes nothing. The same flow applies to a job submission service a quantum research group maintains.

Click through it at your own pace, or open it full screen.

The second demo sets up the Safeguard runner on your own machine, approves it with its device code and then scans from the terminal. That suits teams who keep Qiskit or Cirq notebooks, simulators and pinned requirements files on their own workstations or cluster nodes and want the scan to run where the code lives.

Click through it at your own pace, or open it full screen.

The third demo connects Claude to the Safeguard MCP server with OAuth and lets you choose which tools Claude can use. For a team already using Claude while planning a post-quantum migration, it brings dependency findings for the cryptographic libraries in their projects into the same conversation, limited to the tools they allow.

Click through it at your own pace, or open it full screen.

To try it on your own repositories, download Safeguard and follow the CLI documentation.

Quick check

Sources

• Koch et al., Charge-insensitive qubit design derived from the Cooper pair box, Physical Review A 76, 042319 (October 2007)
• Motzoi, Gambetta, Rebentrost and Wilhelm, Simple pulses for elimination of leakage in weakly nonlinear qubits, Physical Review Letters 103, 110501 (September 2009); arXiv 0901.0534
• Krantz et al., A quantum engineer's guide to superconducting qubits, Applied Physics Reviews (June 2019); arXiv 1904.06560
• Blais, Grimsmo, Girvin and Wallraff, Circuit quantum electrodynamics, Reviews of Modern Physics 93, 025005 (May 2021)
• Walter et al., Rapid high-fidelity single-shot dispersive readout of superconducting qubits, Physical Review Applied 7, 054020 (May 2017); arXiv 1701.06933
• Krinner et al., Engineering cryogenic setups for 100-qubit scale superconducting circuit systems, EPJ Quantum Technology (May 2019); arXiv 1806.07862
• Bluefors, dilution refrigerator measurement systems, product specifications
• Google Quantum AI, Willow spec sheet (9 December 2024), PDF
• Google Quantum AI and collaborators, Quantum error correction below the surface code threshold, Nature 638, 920 to 926 (online 9 December 2024)
• IBM Quantum documentation, processor types
• IBM Quantum documentation, fractional gates
• IBM Quantum documentation, transpiler stages
• IBM Quantum documentation, introduction to transpilation
• IBM Quantum documentation, migrate from Qiskit Pulse to fractional gates
• Cross et al., OpenQASM 3: A broader and deeper quantum assembly language (2021); arXiv 2104.14722
• Moses et al., A race-track trapped-ion quantum processor, Physical Review X 13, 041052 (December 2023)
• Quantinuum, Helios: a 98-qubit trapped-ion quantum computer, arXiv 2511.05465 (November 2025)
• A 98-qubit trapped-ion quantum computer with all-to-all connectivity, Nature 655, 81 to 86 (June 2026)
• Demonstration of logical qubits and repeated error correction with better-than-physical error rates, arXiv 2404.02280 (April 2024)
• Evered et al., High-fidelity parallel entangling gates on a neutral-atom quantum computer, Nature 622, 268 to 272 (October 2023)
• Bluvstein et al., Logical quantum processor based on reconfigurable atom arrays, Nature 626, 58 to 65 (December 2023)
• Xue et al., Quantum logic with spin qubits crossing the surface code threshold, Nature 601, 343 to 347 (January 2022)
• A manufacturable platform for photonic quantum computing, Nature 641, 876 to 883 (February 2025)
• Shor, Polynomial-time algorithms for prime factorization and discrete logarithms on a quantum computer, SIAM Journal on Computing (October 1997)
• Gidney, How to factor 2048 bit RSA integers with less than a million noisy qubits, arXiv 2505.15917 (May 2025)
• NIST, FIPS 203, Module-Lattice-Based Key-Encapsulation Mechanism Standard (13 August 2024)
• NIST, IR 8547 initial public draft, Transition to Post-Quantum Cryptography Standards (12 November 2024)

Last reviewed: 25 October 2026. Hardware figures change with every processor revision; check the linked papers and vendor documentation for the latest measured values.