HBM memory and TSMC packaging: what limits AI chip supply in 2026

AI chip supply in 2026 is limited less by the processor itself than by two parts around it: high bandwidth memory (HBM) and the advanced packaging that joins memory to the processor. Both are concentrated in a few companies, both are expanding fast, and both are still reported as tight.

When an AI company says it cannot get enough capacity, the cause is often not a shortage of designs. A chip needs a processor die, several stacks of specialised memory, and a way to bond them into one package. Each of those steps has few suppliers and long lead times. This post explains the three pieces in plain terms, gives the sourced numbers with dates, and shows where the evidence is weak. All figures are as of 19 October 2026 unless another date is given.

Key numbers at a glance

• HBM supplier shares of revenue, full year 2025: SK hynix 63.2 percent, Samsung 19.3 percent, Micron 17.4 percent (IDC, as cited in an SK hynix filing, per Silicon Analysts).
• HBM revenue shares, second quarter 2026: SK hynix 50 percent, Samsung 33, Micron 18 (Counterpoint Research, 3 September 2026).
• HBM revenue shares, first quarter 2026: SK hynix 58 percent, Samsung 21, Micron 21; second quarter 2025: 64, 15 and 21 (same Counterpoint release).
• SK hynix, quarter ended June 2026: revenue 79.3 trillion won (about $55 billion) and operating profit 60.5 trillion won, both records (SK hynix release, 29 July 2026). It says it began mass shipments of HBM4 in the quarter and has long term supply agreements with about 10 customers.
• Micron, fiscal fourth quarter 2026 (ended 3 September 2026): revenue $54.23 billion, with Cloud Memory unit revenue of $16.283 billion (Micron release, 30 September 2026). Micron no longer reports HBM separately.
• Micron CEO statement: agreements completed for "the vast majority" of calendar 2027 HBM supply, at significant price increases (as quoted by The Next Platform).
• CoWoS packaging capacity at TSMC in 2026: 120,000 to 140,000 wafers per month, a record, with another 50,000 to 60,000 from outside packaging partners (Economic Daily News report, via TrendForce, 15 June 2026). This is a report, not company guidance.
• CoWoS supply gap: about 20 percent now, expected to narrow to about 10 percent by end 2026 (same report).
• CoWoS outlook: about 130,000 wafers per month by end 2026 doubling to 260,000 by end 2028 (Economic Daily News, citing supply chain sources, via TrendForce, 14 September 2026). A report, not TSMC guidance.
• TSMC's own forecasts: AI accelerator wafer demand up 11 times from 2022 to 2026, and CoWoS capacity growing more than 80 percent a year from 2022 to 2027 (TSMC Technology Symposium, May 2026, via TrendForce).
• Nvidia supply and capacity obligations: $105 billion (Nvidia, quarter ended 26 July 2026).
• Amazon 2026 capital spending guide: about $220 billion, up from about $200 billion, which Andy Jassy attributed to higher memory costs (Amazon call, 30 July 2026).

The three parts of an AI chip

Think of a modern AI accelerator as a small city. The processor die is the factory. HBM is the warehouse right beside it. The package is the road system joining them. A fast factory with a slow warehouse or no road does not help.

The processor die is made at a foundry, a factory that makes chips designed by others. For many AI chips that foundry is TSMC in Taiwan. Microsoft's Maia 200, for example, is built on TSMC's 3 nanometer process.

HBM is memory built as a tall stack of thin chips, joined vertically and sitting next to the processor. It is much faster than ordinary server memory because it has a very wide connection to the processor. Silicon Analysts lists HBM4, the newest generation, as having a 2,048 bit interface against 1,024 for the previous HBM3E, and 1.5 to 2 TB per second of bandwidth per stack against 896 to 1,280 GB per second. A stack of memory chips is also hard to make: more layers means more chances for a flaw, which lowers the share of usable parts, called yield.

Packaging is the step that puts the processor die and the HBM stacks together on a shared base. TSMC's version is called CoWoS, short for chip on wafer on substrate. In plain terms, the processor and memory stacks sit side by side on a thin slice of silicon that carries thousands of tiny wires between them. The industry term for this class of packaging is 2.5D packaging. It is a separate production line from making the chip, and it has been a bottleneck.

Why memory matters so much for inference

Running a model, called inference, tends to be limited by how fast the chip can read the model's data, not by how fast it can multiply. That is why newer inference chips carry a lot of memory. Google's TPU 8i has 288 GB of HBM, Microsoft's Maia 200 has 216 GB, and both add hundreds of megabytes of on-chip memory to cut waiting. See Google TPU 8t and 8i explained.

SK hynix said in its July results that it expects the spread of AI inference to keep raising demand for HBM, standard DRAM and NAND flash storage. Demand for memory is rising for reasons that go beyond training new models.

HBM: three suppliers, shifting shares

Only three companies make HBM at scale: SK hynix and Samsung of South Korea, and Micron of the United States. Their relative positions are changing.

Counterpoint Research published quarterly HBM revenue shares on 3 September 2026:

• Q2 2025: SK hynix 64 percent, Samsung 15, Micron 21.
• Q1 2026: 58, 21 and 21.
• Q2 2026: 50, 33 and 18.

For the full year 2025, Silicon Analysts relays an IDC figure, cited in an SK hynix filing, of SK hynix 63.2 percent, Samsung 19.3 and Micron 17.4. Silicon Analysts also notes that Counterpoint revised its Samsung first quarter figure in early October 2026; the numbers above are those on Counterpoint's own page as of 19 October 2026.

The direction is that SK hynix's lead is narrowing while Samsung rises. Counterpoint says most HBM revenue still comes from HBM3E, that HBM4 shipments should become clearly visible from the second half of 2026, and that it expects Samsung's share to rise gradually as its HBM4 shipments grow. That last point is a forecast. Two cautions apply to all of these figures. Shares are of revenue, so price differences count. And they are third party estimates, not company disclosures. For the Korean makers in more depth, see Korea's memory makers and the HBM boom.

A separate earlier set of figures, reported by a Korean outlet and relayed by Astute Group in September 2025, put the second quarter of 2025 at SK hynix 62, Micron 21 and Samsung 17. Different firms and periods give different numbers, so only compare figures from the same source.

HBM4 is the generation tied to Nvidia's Vera Rubin platform. SK hynix says it began mass shipments of HBM4 in the June quarter and will ramp in the second half of 2026, and that it has shipped HBM4E samples. Micron's CEO described the HBM4 ramp as "proceeding apace" and mentioned a custom HBM4E product developed with Nvidia. Silicon Analysts reports, citing Korean media via another outlet, that SK hynix priced HBM4 about 70 percent above HBM3E in early Nvidia talks. That is a report, not a confirmed price, and none of the memory makers publishes a per stack price.

Memory is sold years ahead

Two features of the memory business shape supply.

First, long term agreements. SK hynix says it has signed long term agreements with about 10 customers. Blocks and Files describes these as customers making financial commitments in return for guaranteed chip supply. Micron's CEO said, as quoted by The Next Platform, that Micron has completed agreements for the vast majority of its calendar 2027 HBM supply with significant price increases. Micron's CEO also said memory will be tightly constrained in 2027 and 2028, and the company's other disclosures include customer prepayments of $32 billion and $150 billion of remaining performance obligations, though these cover all memory products, not HBM alone.

Second, HBM crowds out ordinary memory. Reuters, as relayed by Blocks and Files, said SK hynix did not make enough conventional DRAM to capture the price rise, because it used DRAM bits in HBM products. When memory makers favour HBM, the supply of ordinary server and PC memory tightens too.

The cost reaches the buyers. Jassy said Amazon raised its 2026 capital spending guide by roughly $20 billion because of higher memory costs, and that new contracts reflect current costs while existing multi year deals keep agreed prices. That is one company's explanation of one budget line.

Packaging: CoWoS and the 20 percent gap

TSMC's CoWoS capacity has expanded very fast. According to a report from Taiwan's Economic Daily News summarised by TrendForce on 15 June 2026, TSMC's monthly capacity in 2026 is 120,000 to 140,000 wafers, a record, plus 50,000 to 60,000 more from outside packaging partners. That brings the industry near 200,000 wafers per month. TSMC itself forecast, at its May 2026 Taiwan Technology Symposium as reported by Reuters and relayed by TrendForce on 14 May 2026, a CoWoS capacity growth rate of more than 80 percent a year from 2022 to 2027, and said demand for AI accelerator wafers would grow 11 times between 2022 and 2026. A wafer is the round slice of silicon on which chips are made, so wafers per month is the standard way to measure output.

The same TrendForce item says the gap between supply and demand is about 20 percent and is expected to narrow to about 10 percent by the end of 2026, and that TrendForce expects the severe shortage to start easing in 2027, helped by orders spilling to other packagers and by TSMC's expansion. The 20 and 10 percent figures come from the Taiwanese newspaper citing institutional investors. They are not TSMC statements.

Further out, a September report from the Economic Daily News, citing supply chain sources and summarised by TrendForce on 14 September 2026, said CoWoS capacity could reach about 130,000 wafers per month by the end of 2026 and double to about 260,000 by the end of 2028, with growth centred on TSMC's AP7 site in Taiwan and its Arizona campus. Packaging in Arizona would mean fewer advanced chips shipped back to Taiwan to be finished. These are newspaper figures, not TSMC guidance, and they sit slightly apart from the June report's range.

Demand is concentrated. Nvidia reports $105 billion in supply and capacity obligations, which are promises to pay suppliers for capacity. Published estimates of how much CoWoS capacity Nvidia holds disagree, and no primary figure is available, so none is given here.

Bigger packages, more memory per chip

Packaging is not only getting more plentiful. It is getting larger, which raises how much memory one accelerator can carry. The size limit is set by the reticle, the area a lithography machine can print in one exposure, roughly the size of a large postage stamp. To build something bigger than one reticle, the silicon base under the chips is stitched from several exposures.

At the May 2026 symposium, as reported by Taiwan's Commercial Times and relayed by TrendForce, TSMC's mass produced CoWoS was a 5.5 reticle version, described as the largest in production, with a reported 98 percent yield. The same report said a 14 reticle version holding 20 HBM stacks is planned for 2028, and a still larger version supporting up to 24 stacks for 2029. TSMC also described a wafer scale approach, called System on Wafer, with more than 40 reticles and up to 64 HBM stacks, targeted for 2029 in a version that includes HBM.

The practical meaning is that each new generation of package asks for more HBM stacks per chip. So even as packaging capacity grows, the demand for memory per accelerator grows with it, which is one reason supply can stay tight while capacity expands.

What this means for custom chips and Nvidia alike

Custom chips and Nvidia GPUs draw on the same pools. Both need TSMC wafers, HBM and advanced packaging. A custom chip does not escape these limits, and Broadcom's customers and Nvidia's customers compete for the same capacity. That is one reason the large buyers sign multi year deals and talk about gigawatts. See AI chip market share 2026 and OpenAI's compute commitments for how this shows up in contracts.

What is firm and what is uncertain

Firm, because companies reported it:

• SK hynix's and Micron's results, SK hynix's HBM4 shipment start and its long term agreements.
• Nvidia's stated supply obligations and Amazon's capex guide and its stated reason.
• The technical specs of HBM4 as published by memory makers and relayed by Silicon Analysts.

Uncertain:

• HBM market shares. Three different firms give different numbers, and Counterpoint's were revised in October.
• CoWoS capacity and the size of the shortage, which are newspaper and analyst figures.
• HBM prices, which no supplier states directly.
• Silicon Analysts also lists estimated HBM cost per accelerator, roughly 47 percent of manufacturing cost for some Nvidia parts. These are its estimates, so do not rely on them.
• Anything about 2027 and 2028. It is a projection.

This is not investment advice, and nothing here predicts prices or supply.

What to watch next

• Samsung's HBM4 progress and whether its share gain holds in the third quarter 2026 figures.
• Whether the CoWoS gap really narrows to about 10 percent by the end of 2026, and whether reported capacity reaches about 130,000 wafers per month.
• HBM price moves in 2027 contracts.
• SK hynix's Yongin cleanroom, expected to open in early 2027 per its release, and its packaging plant plans.
• Whether memory costs keep pushing up cloud capital spending guides.

For teams buying software and cloud services, supply limits show up as waiting lists and price rises. Safeguard offers SBOM and dependency scanning and a free scan at gold.safeguard.sh/scan for the software side of your estate.

Quick check

Sources

• TrendForce, TSMC CoWoS supply and demand gap (15 June 2026): https://www.trendforce.com/news/2026/06/15/news-tsmc-cowos-supply-demand-gap-reportedly-seen-narrowing-from-20-to-10-by-end-2026-as-capacity-expands/
• Counterpoint Research, global HBM market share Q2 2026 (3 September 2026): https://counterpointresearch.com/ko/insights/global-hbm-market-share-q2-2026
• TrendForce, TSMC sees AI wafer demand rising 11 times (14 May 2026): https://www.trendforce.com/news/2026/05/14/news-tsmc-sees-ai-wafer-demand-rising-11x-from-2022-2026-targets-cowos-with-24-hbm-stacks-in-2029/
• TrendForce, CoWoS to double by 2028 (14 September 2026): https://www.trendforce.com/news/2026/09/14/news-tsmc-reportedly-targets-22-2nm-16-3nm-capacity-boost-by-mid-2027-cowos-to-double-by-2028/
• Silicon Analysts, HBM4 market share race: https://siliconanalysts.com/analysis/hbm4-market-share-race-2026
• Astute Group, HBM share (September 2025): https://www.astutegroup.com/news/general/sk-hynix-holds-62-of-hbm-micron-overtakes-samsung-2026-battle-pivots-to-hbm4/
• SK hynix Q2 2026 results (Pulse 2): https://pulse2.com/sk-hynix-reports-record-q2-2026-revenue-of-79-3-trillion-won-about-55-2-billion/
• Blocks and Files, SK hynix Q2 2026: https://www.blocksandfiles.com/flash/2026/07/29/sk-hynix-announces-extraordinarily-high-revenues-but-misses-expectations/5280499
• Micron fiscal Q4 2026 release (SEC): https://www.sec.gov/Archives/edgar/data/0000723125/000072312526000018/a2026q4ex991-pressrelease.htm
• The Next Platform, Micron and HBM4: https://www.nextplatform.com/a/5300701
• Nvidia Q2 FY2027 coverage (The Energy Mag): https://theenergymag.com/news/market-news/nvidia-q2-revenue-hits-96-2-b-as-data-center-surges-117-and-vera-rubin-ramps
• Amazon Q2 2026 call summary (Webull): https://www.webull.com/news/15364638750483456
• Google, eighth generation TPUs: https://blog.google/innovation-and-ai/infrastructure-and-cloud/google-cloud/eighth-generation-tpu-agentic-era/
• Microsoft, Maia 200: https://blogs.microsoft.com/blog/2026/01/26/maia-200/

Last reviewed: 19 October 2026.