CWE-1431 is a hardware module implementing a cryptographic algorithm that writes sensitive information about intermediate state or results to one of its output wires, typically the port that carries the final result.
It is a chip design weakness, relevant to teams building system on chip cryptographic blocks.
How it happens
A cipher can be mathematically sound and still be weakened by its implementation. MITRE's point is that the security assumptions break if a hardware module leaks intermediate encryption state or results where an attacker can observe them.
The leak is on the output wires themselves, typically the port that carries the final result, which can show intermediate values while the operation is still running.
What an attacker gains
MITRE lists confidentiality: reading memory or application data. The record gives no CVE examples.
How to find it
MITRE lists several methods for register transfer level (RTL) designs:
- Automated static analysis of RTL source, without simulating it or using formal verification.
- Simulation or emulation of RTL with assertions about relevant signal values.
- Formal verification, exhaustively checking whether an assertion holds for a design.
- Manual analysis, tracing data flow from intermediate signals to outputs.
How to fix it
MITRE rates the following high at both design and implementation time. Add or change control flow logic along data paths connecting sources, meaning signals with intermediate cryptographic state, to sinks, meaning module outputs and other signals outside the trusted cryptographic zone. Let results reach sinks only when conditions are right, typically when the final result is ready. Otherwise drive a safe default value.
Quick check
What should an output show before the final result is ready?
A safe default value, not intermediate cryptographic state.
