CWE-1421 is about a processor event that lets transient operations access architecturally restricted data, for example data in another address space, in a shared microarchitectural structure such as a CPU cache. The data can then be exposed over a covert channel.
It is a hardware weakness with software consequences, so it concerns chip designers, system software vendors and anyone relying on process, kernel or enclave boundaries.
How it happens
Commodity processors offer features that keep software components apart: memory segmentation, virtual memory, privilege rings, trusted execution environments and virtual machines. Virtual memory, for instance, stops one process reading another's private data.
Those same processors also share microarchitectural resources that cache data, across SMT threads, privilege rings and other contexts. When transient operations can reach protected data that sits in one of those shared resources, the boundary the architecture promised is no longer a boundary.
Observed examples in the record:
- CVE-2017-5715: a fault may allow transient user mode operations to access kernel data cached in the L1D.
- CVE-2018-3615: a fault may allow transient non enclave operations to access SGX enclave data cached in the L1D.
- CVE-2019-1135: a TSX Asynchronous Abort may allow transient operations to access architecturally restricted data.
What an attacker gains
Confidentiality only: reading memory, with medium likelihood. That can still mean kernel or enclave secrets.
How to find it
- Manual analysis. Inspect processor specifications for predictors, out of order access checks and similar features.
- Taint analysis. In hardware, static or dynamic taint analysis can label data in one context, such as kernel data, and look for information flow into another.
- Vendor tools. After a weakness is known, tools can attempt to transiently execute a vulnerable code sequence and check whether it leaks data.
- Fuzzing. Researchers have shown black box fuzzing of hardware can detect it, though MITRE says it is opportunistic and may miss some.
How to fix it
MITRE separates hardware and software measures.
- Engineer the pipeline so architecturally restricted data cannot be used by operations that execute transiently. Rated high.
- Do not share resources that can hold sensitive data, such as fill buffers and store buffers. Rated moderate. This is effective across SMT threads or cores, but less practical between contexts on the same thread, such as user and kernel.
- Sanitize state on a context change such as a system call. Rated moderate, and not enough alone for asynchronous sharing between SMT threads.
- Isolate contexts in software. Kernel page table isolation, for example, mitigates Meltdown by separating user mode and kernel mode page tables. Rated limited, because it only works for some weaknesses.
- Block covert channels in hardware. Rated limited, since many channels exist outside the data cache.
- Compiler changes that avoid generating the affected instructions where one instruction or a small set is responsible.
Quick check
What is the shared structure in this weakness?
A microarchitectural resource such as a CPU cache or buffer that holds data and is shared across contexts like SMT threads or privilege rings.
