CWE-1332 covers devices that lack, or incorrectly implement, circuitry or sensors to detect and mitigate the skipping of security-critical CPU instructions. Firmware authors and chip designers both own part of it.
How it happens
Operating conditions can change in ways that cause instructions to be skipped, through electrical disturbance or running outside expected conditions. Security code often hinges on one conditional branch, such as accepting or rejecting a password. In the binary that is usually a single branch instruction. If it is skipped, the branch condition is effectively flipped and the wrong path runs.
This hits firmware authentication, password verification and other security decision points. Attackers use fault injection to make skips happen more often or more reliably than they would naturally.
The record includes CVE-2019-15894: a fault injection attack bypassed the verification mode, potentially allowing arbitrary code execution.
What an attacker gains
Bypass of protection mechanisms, altered execution logic and an unexpected state, affecting confidentiality, integrity and authentication.
How to find it
MITRE lists three methods, each at moderate effectiveness:
- Static analysis, once a developer has marked which code paths are critical.
- Emulation of a CPU with instruction skips, or RTL simulation of CPU IP, to show which code is sensitive to skips.
- Manual analysis against security objectives, less precise than emulation especially above assembly level.
How to fix it
- Design for safe failure when inputs such as Vcc go outside acceptable ranges.
- Design for safe behavior if instructions are skipped.
- Identify mission critical secrets to wipe when faulting is detected, and build the deletion mechanism.
- Add redundancy by repeating an operation in space or time and using majority voting. Make conditional instruction timing unpredictable.
- Use redundant operations or canaries to detect and respond to faults.
- Check that fault mitigations are strong in practice. A low power detector that takes 50 clock cycles to trigger may be too slow if the instruction counter has already moved on.
A software sketch of redundancy in C:
/* Check the critical condition twice, with a different form each time */
int ok1 = (memcmp(calc, expected, 32) == 0);
int ok2 = (memcmp(calc, expected, 32) != 0) ? 0 : 1;
if (ok1 && ok2) {
boot_image();
} else {
wipe_secrets();
halt();
}
This raises the effort for a single glitch but does not replace hardware detection. Compilers can optimize away naive duplication, so inspect the generated code.
Quick check
Why is a single branch instruction a weak point?
If a fault skips it, the condition is effectively inverted and the wrong security branch executes.
