CWE-1280 describes a hardware based access control check that occurs after the asset has been accessed. Chip designers working in Verilog or VHDL are the main audience.
How it happens
The product implements a hardware access control check, and the asset should only be reachable once the check succeeds. If the operation is not atomic, and the asset is touched before the check completes, security is compromised.
It is the same shape as a time-of-check problem in software, only in logic. The check exists and is correct, but it runs too late to matter. This also resembles the pattern in CWE-1264, where data moves before the verdict.
What an attacker gains
The record lists modifying and reading memory and application data, gaining privileges or assuming identity, and bypassing protection mechanisms, with access control and confidentiality and integrity at stake.
How to find it
No detection methods are listed. Review the timing of each protected access. Ask where the asset is read or written and where the verdict is produced, and confirm the access cannot proceed in the same cycle or earlier. Simulate illegal requests and verify that no data moves and no write lands.
How to fix it
- Make the check and the access one atomic step, so the asset is only reachable after success.
- Block the data or write path by default until the check passes.
- Cover denied requests in verification, not just granted ones.
Quick check
The check is correct. Why is this still a flaw?
Because the asset was already accessed. A right answer that arrives late protects nothing.
